NDLI: Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor

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Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams

Evaluating the Imagine Stream Architecture

Field-testing IMPACT EPIC research results in Itanium 2

Wire Delay is Not a Problem for SMT (In the Near Future)

The Vector-Thread Architecture

Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance

Microarchitecture Optimizations for Exploiting Memory-Level Parallelism

Memory Ordering: A Value-Based Approach

Transactional Memory Coherence and Consistency

TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model

SMTp: An Architecture for Next-generation Scalable Multi-threading

A Formal Approach to Frequent Energy Adaptations for Multimedia Applications

Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor

Power Awareness through Selective Dynamically Optimized Traces

X-RAY: A Non-Invasive Exclusive Caching Mechanism for RAIDs

Low-Latency Virtual-Channel Routers for On-Chip Networks

Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism

Adaptive Cache Compression for High-Performance Processors

iWatcher: Efficient Architectural Support for Software Debugging

From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation

Prophet/Critic Hybrid Branch Prediction

Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor

The Case for Lifetime Reliability-Aware Microprocessors

Exploiting Resonant Behavior to Reduce Inductive Noise

Use-Based Register Caching with Decoupled Indexing

A Content Aware Integer Register File Organization

Physical Register Inlining

A First-Order Superscalar Processor Model

Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies

Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs

A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy

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Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor

Content Provider	ACM Digital Library
Author	Weaver, Christopher Emer, Joel Reinhardt, Steven K. Mukherjee, Shubhendu S.
Abstract	Transient faults due to neutron and alpha particle strikes posea significant obstacle to increasing processor transistor counts infuture technologies. Although fault rates of individual transistorsmay not rise significantly, incorporating more transistors into adevice makes that device more likely to encounter a fault. Hence,maintaining processor error rates at acceptable levels will requireincreasing design effort.This paper proposes two simple approaches to reduce errorrates and evaluates their application to a microprocessor instructionqueue. The first technique reduces the time instructions sit invulnerable storage structures by selectively squashing instructionswhen long delays are encountered. A fault is less likely to cause anerror if the structure it affects does not contain valid instructions.We introduce a new metric, MITF (Mean Instructions To Failure),to capture the trade-off between performance and reliability introducedby this approach.The second technique addresses false detected errors. In theabsence of a fault detection mechanism, such errors would nothave affected the final outcome of a program. For example, a faultaffecting the result of a dynamically dead instruction would notchange the final program output, but could still be flagged by thehardware as an error. To avoid signalling such false errors, wemodify a pipeline's error detection logic to mark affected instructionsand data as possibly incorrect rather than immediately signalingan error. Then, we signal an error only if we determine laterthat the possibly incorrect value could have affected the program'soutput.
File Format	PDF
ISBN	0769521436
ISSN	10636897
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2004-06-19
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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