NDLI: Reconfigurable SoC - What Will it Look Like?

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DATE Executive Committee

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Vendors Committee

Technical Program Committee

Welcome to DATE 2002

Best Paper Awards

On Nanoscale Integration and Gigascale Complexity in the Post .Com World

Global Responsibilities in SOC Design

How to Choose Semiconductor IP? - Embedded Processors

Make Your SoC Design a Winner: Select the Right Memory IP

How to Choose Semiconductor IP: Embedded Software

IP Day: How to Choose Semiconductor IP?

Formal Verification of the Pentium® 4 Floating-Point Multiplier

Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-of-Order Microprocessors with a Reorder Buffer

Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units

A Case Study for the Verification of Complex Timed Circuits: IPCMOS

FPGA Placement by Thermodynamic Combinatorial Optimization

An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees

Arbitrary Convex and Concave Rectilinear Module Packing Using TCG

A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits

Exact Grading of Multiple Path Delay Faults

Modeling Techniques and Tests for Partial Faults in Memory Devices

A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults

Low Power Error Resilient Encoding for On-Chip Data Buses

Managing Power Consumption in Networks on Chip

Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Savings States

AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors

IP is All About Implementation and Customer Satisfaction

Using Problem Symmetry in Search Based Satisfiability Algorithms

BerkMin: A Fast and Robust Sat-Solver

Dynamic Scheduling and Clustering in Symbolic Image Computation

Wire Placement for Crosstalk Energy Minimization in Address Buses

Dynamic VTH Scaling Scheme for Active Leakage Power Reduction

Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints

Sizing Power/Ground Meshes for Clocking and Computing Circuit Components

A Signature Test Framework for Rapid Production Testing of RF Circuits

Analog IP Testing: Diagnosis and Optimization

A New Design Flow and Testability Measure for the Generation of a Structural Test and BIST for Analogue and Mixed-Signal Circuits

Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal Ics

E-Design Based on the Reuse Paradigm

Internet-Based Collaborative Test Generation with MOSCITO

A Two-Tier Distributed Electronic Design Framework

Embedded System Design Based On Webservices

Who Owns the Platform?

IP for Embedded Robustness

Embedded Diagnosis IP

Embedded Robustness Ips

CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines

Generalized Early Evaluation in Self-Timed Circuits

Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constraint

A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics

Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits

Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices

Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification

EDA Tools for RF: Myth or Reality?

Dynamic Runtime Re-Scheduling Allowing Multiple Implementations of a Task for Platform-Based Designs

Techniques to Evolve a C++ Based System Design Language

A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects

Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications

Global Optimization Applied to the Oscillator Problem

MEDEA+ and ITRS Roadmaps

A Burst-Mode Oriented Back-End for the Balsa Synthesis System

Detecting State Coding Conflicts in STGs Using Integer Programming

Verifying Clock Schedules in the Presence of Cross Talk

Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach

Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter

Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip

An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs

Gate Level Fault Diagnosis in Scan-Based BIST

An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment

Reducing Test Application Time Through Test Data Mutation Encoding

Hardware/Software Trade-Offs for Advanced 3G Channel Coding

An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs

Assigning Program and Data Objects to Scratchpad for Energy Reduction

Networks on Chip: A New Paradigm for Systems on Chip Design

Communication Mechanisms for Parallel DSP Systems on a Chip

Networks on Silicon: Combining Best-Effort and Guaranteed Services

Data Reuse Exploration Techniques for Loop-Dominated Applications

EAC: A Compiler Framework for High-Level Energy Estimation and Optimization

Power Savings in Embedded Processors through Decode Filer Cache

Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors

Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model

Hierarchical Current Density Verification for Electromigration Analysis in Arbitrary Shaped Metallization Patterns of Analog Circuits

A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem

Test Planning and Design Space Exploration in a Core-Based Environment

A Hierarchical Test Scheme for System-On-Chip Designs

Efficient Wrapper/TAM Co-Optimization for Large SOCs

Beyond UML to an End-of-Line Functional Test Engine

Event Model Interfaces for Heterogeneous System Analysis

Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems

A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems

Automatic Evaluation of the Accuracy of Fixed-Point Algorithms

Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs

A Video Compression Case Study on a Reconfigurable VLIW Architecture

A Complete Data Scheduler for Multi-Context Reconfigurable Architectures

Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications

(Self-)reconfigurable Finite State Machines: Theory and Implementation

A Linear-Centric Simulation Framework for Parametric Fluctuations

Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio

Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets

High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions

Effective Software Self-Test Methodology for Processor Cores

Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression

Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression

Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths

Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design

Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses

A Linear-Centric Modeling Approach to Harmonic Balance Analysis

An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor

Design Automation for Deepsubmicron: Present and Future

Reconfigurable SoC - What Will it Look Like?

Congestion-Aware Logic Synthesis

Layout Driven Decomposition with Congestion Consideration

Improving Placement under the Constant Delay Model

Crosstalk Alleviation for Dynamic PLAs

Flip-Flop and Repeater Insertion for Early Interconnect Planning

Congestion Estimation with Buffer Planning in Floorplan Design

Maze Routing with Buffer Insertion under Transition Time Constraints

Optimal Transistor Tapering for High-Speed CMOS Circuits

Incremental Diagnosis and Correction of Multiple Faults and Errors

Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults

FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis

An Environment for Dynamic Component Composition for Efficient Co-Design

Functional Verification for SystemC Descriptions Using Constraint Solving

The Modelling of Embedded Systems Using HASoC

A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems

The Real-Time UML Standard: Definition and Application

UML for Embedded Systems Specification and Design: Motivation and Overview

A UML-Based Design Methodology for Real-Time and Embedded Sytems

Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processor

A Dynamic Voltage Scaling Algorithm for Dynamic-Priority Hard Real-Time Systems Using Slack Time Analysis

Extending Synchronous Languages for Generating Abstract Real-Time Models

An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach

Closed-Form Crosstalk Noise Metrics for Physical Design Applications

Formulation of Low-Order Dominant Poles for Y-Matrix of Interconnects

Library Compatible Ceff for Gate-Level Timing

Self-Checking Scheme for the On-Line Testing of Power Supply Noise

Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance

Exploiting Idle Cycles for Algorithm Level Re-Computing

New Techniques for Speeding-Up Fault-Injection Campaigns

System Design for Flexibility

Accurate Area and Delay Estimators for FPGAs

A Powerful System Design Methodology Combining OCAPI and Handel-C for Concept Engineering

Automated Concurrency Re-Assignment in High Level System Models for Efficient System-Level Simulation

From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications

Memory System Connectivity Exploration

Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory

Multiple-Precision Circuits Allocation Independent of Data-Objects Length

Efficient Model Reduction of Linear Time-Varying Systems via Compressed Transient System Function

Passive Constrained Rational Approximation Algorithm Using Nevanlinna-Pick Interpolation

Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods

An Optimal Algorithm for the Automatic Generation of March Tests

Minimal Test for Coupling Faults in Word-Oriented Memories

Maximizing Impossibilities for Untestable Fault Identification

Automated Modeling of Custom Digital Circuits for Test

False Path Elimination in Quasi-Static Scheduling

A Data Analysis Method for Software Performance Prediction

A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications

A Compiler-Based Approach for Improving Intra-Iteration Data Reuse

European CAD from the 60's to the New Millenium

Design Technology for Networked Reconfigurable FPGA Platforms

High-Speed Non-Linear Asynchronous Pipelines

Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding

Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis

Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models

Hierarchical Simulation of Substrate Coupling in Mixed-Signal ICs Considering the Power Supply Network

Fast Method to Include Parasitic Coupling in Circuit Simulations

Accurate Estimating Simultaneous Switching Noises by Using Application Specific Device Modeling

Macromodeling of Digital I/O Ports for System EMC Assessment

Formal Verification Techniques: Industrial Status and Perspectives

Low Power Embedded Software Optimization Using Symbolic Algebra

An Adaptive Dictionary Encoding Scheme for SOC Data Buses

Power Efficient Embedded Processor Ip's through Application-Specific Tag Compression in Data Caches

Systematic Power-Performance Trade-Off in MPEG-4 by Means of Selective Function Inlining Steered by Address Optimization Opportunities

An Approach to Model Checking for Nonlinear Analog Systems

Speeding up SAT for EDA

Search-Based SAT Using Zero-Suppressed BDDs

An Encoding Technique for Low Power CMOS Implementations of Controllers

Composition Trees in Finding Best Variable Orderings for ROBDDs

A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs

Concurrent and Selective Logic Extraction with Timing Consideration

Improved Technology Mapping for PAL-Based Devices Using a New Approach to Multi-Output Boolean Functions

Efficient and Effective Redundancy Removal for Million-Gate Circuits

Visualization of Partial Order Models in VLSI Design Flow

High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems

Power-Efficient Trace Caches

Reducing Cache Access Energy in Array-Intensive Applications

The Use of Runtime Configuration Capabilities for Networked Embedded Systems

A SAT Solver Using Software and Reconfigurable Hardware

A New Time Model for the Specification, Design, Validation and Synthesis of Embedded Real-Time Systems

Improved Constraints for Multiprocessor System Scheduling

Maximizing Conditonal Reuse by Pre-Synthesis Transformations

Control Circuit Templates for Asynchronous Bundled-Data Pipelines

Transforming Arbitrary Structures into Topologically Equivalent Slicing Structures

A New Formulation for SOC Floorplan Area Minimization Problem

Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design

EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses

Estimation of Power Consumption in Encoded Data Buses

Optimization Techniques for Design of General and Feedback Linear Analog Amplifier with Symbolic Analysis

Critical Comparison among Some Analog Fault Diagnosis Procedures Based on Symbolic Techniques

The Selective Pull-Up (SP) Noise Immunity Scheme for Dynamic Circuits

Substrate Parasitic Extraction for RF Integrated Circuits

A Complete Phase-Locked Loop Power Consumption Model

Statistical Timing Driven Partitioning for VLSI Circuits

DAISY-CT: A High-Level Simulation Tool for Continuous-Time Delta Sigma Modulators

Automated Optimal Design of Switched-Capacitor Filters

On-Chip Inductance Models: 3D or Not 3D?

Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate

Compact Macromodel for Lossy Coupled Transmission Lines

An EMC-Compliant Design Method of High-Density Integrated Circuits

Finding a Common Fault Response for Diagnosis during Silicon Debug

IDDT Testing of Embedded CMOS SRAMs

Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis

An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits

On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems

Directed-Binary Search in Logic BIST Diagnostics

An Evolutionary Approach to the Design of On-Chip Pseudorandom Test Pattern Generators

Fault Isolation Using Tests for Non-Isolated Blocks

A Heuristic for Test Scheduling at System Level

Formulation of SOC Test Scheduling as a Network Transportation Problem

A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-Based FPGAs

Efficient On-Line Testing Method for a Floating-Point Iterative Array Divider

An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores

The Fraunhofer Knowledge Network (FKN) for Training in Critical Design Disciplines

Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments

FlexBench: Reuse of Verification IP to Increase Productivity

Mappability Estimation of Architecture and Algorithm

Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS

A Parallel LCC Simulation System

Error Simulation Based on the SystemC Design Description Language

Towards a Kernel Language for Heterogeneous Computing

Top-Down System Level Design Methodology Using SpecC, VCC and SystemC

Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors

Steady State Calculation of Oscillators Using Continuation Methods

Call for Papers DATE 2003

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