NDLI: Future performance challenges in nanometer design

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The electronics industry supply chain (panel session): who does what?

Future performance challenges in nanometer design

IC design in high-cost nanometer-technologies era

LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs

Robust interfaces for mixed-timing systems with application to latency-insensitive protocols

Latency-driven design of multi-purpose systems-on-chip

Estimation of speed, area, and power of parameterizable, soft IP

Formal property verification by abstraction refinement with formal, simulation and hybrid engines

Scalable hybrid verification of complex microprocessors

Symbolic RTL simulation

A unified DFT architecture for use with IEEE 1149.1 and VSIA/IEEE P1500 compliant test access controllers

Instruction-level DFT for testing processor and IP cores in system-on-a-chip

Test strategies for BIST at the algorithmic and register-transfer levels

The next HDL (panel session): if C++ is ;the answer, what was the question?

Reticle enhancement technology: implications and challenges for physical design

Enabling alternating phase shifted mask designs for a full logic gate level: design rules and design rule checking

Layout design methodolgies for sub-wavelength manufacturing

Adoption of OPC and the impact on design and layout

Adoption of OPC and the impact on design and layout

Practical application of full-feature alternating phase-shifting technology for a phase-aware standard-cell design flow

Practical application of full-feature alternating phase-shifting technology for a phase-aware standard-cell design flow

Layout-driven hot-carrier degradation minimization using logic restructuring techniques

An algorithm for bi-decomposition of logic functions

Factoring and recognition of read-once functions using cographs and normality

Logic minimization using exclusive OR gates

Design of half-rate clock and data recovery circuits for optical communication systems

A novel method for stochastic nonlinearity analysis of a CMOS pipeline ADC

Behavioral partitioning in the synthesis of mixed analog-digital systems

Efficient DDD-based symbolic analysis of large linear analog circuits

Random limited-scan to improve random pattern testing of scan circuits

Test volume and application time reduction through scan chain concealment

An approach to test compaction for scan circuits that enhances at-speed testing

Generating efficient tests for continuous scan

Combining low-power scan testing and test data compression for system-on-a-chip

Your core— my problem? (panel session): integration and verification of IP

A quick safari through the reconfiguration jungle

Re-configurable computing in wireless

Hardware/software instruction set configurability for system-on-chip processors

A practical methodology for early buffer and wire resource allocation

Creating and exploiting flexibility in steiner trees

Simultaneous shield insertion and net ordering under explicit RLC noise constraint

On optimum switch box designs for 2-D FPGAs

Dependency preserving probabilistic modeling of switching activity using bayesian networks

A static estimation technique of power sensitivity in logic circuits

JouleTrack: a web based tool for software energy profiling

Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW

Circuit-based Boolean Reasoning

Checking equivalence for partial implementations

Validating the intel pentium 4 microprocessor

Nuts and bolts of core and SoC verification

Teaching future verification engineers: the forgotten side of logic design

SoC integration of reusable baseband bluetooth IP

One-chip bluetooth Asic challenges

Transformations for the synthesis and optimization of asynchronous distributed control

Speculation techniques for high level synthesis of control intensive designs

Parallelizing DSP nested loops on reconfigurable architectures using data context switching

Using symbolic algebra in algorithmic level DSP synthesis

Computing logic-stage delays using circuit simulation and symbolic elmore analysis

A new gate delay model for simultaneous switching and its applications

Static timing analysis including power supply noise effect on propagation delay in VLSI circuits

Simulation-based test algorithm generation and port scheduling for multi-port memories

Improving bus test via IDDT and boundary scan

Fault characterizations and design-for-testability technique for detecting \$I_{DDQ}\$ faults in CMOS/BiCMOS circuits

Testing for interconnect crosstalk defects using on-chip embedded processor cores

(When) will FPGAs kill ASICs? (panel session)

Inductance 101: modeling and extraction

Inductance 101: analysis and design issues

Modeling magnetic coupling for on-chip interconnect

Min/max on-chip inductance models and delay metrics

Utilizing memory bandwidth in DSP embedded processors

Address code generation for digital signal processors

Reducing memory requirements of nested loops for embedded systems

Detection of partially simultaneously alive signals in storage requirement estimation for data intensive applications

A new structural pattern matching algorithm for technology mapping

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

Latency and latch count minimization in wave steered circuits

Performance-driven multi-level clustering with application to hierarchical FPGA mapping

Application of constraint-based heuristics in collaborative design

A universal client for distributed networked design and computing

Hypermedia-aided design

A framework for object oriented hardware specification, verification, and synthesis

When will the analog design flow catch up with digital methodology? (panel session)

Achieving 550 MHz in an ASIC methodology

A semi-custom design flow in high-performance microprocessor design

Reducing the frequency gap between ASIC and custom designs: a custom perspective

Low-energy intra-task voltage scheduling using static timing analysis

Battery-aware static scheduling for distributed real-time embedded systems

An approach to incremental design of distributed embedded systems

Signal representation guided synthesis using carry-save adders for synchronous data-path circuits

Improved merging of datapath operators using information content and required precision analysis

Digital filter synthesis based on minimal signed digit representation

Publicly detectable techniques for the protection virtual components

Watermarking of SAT using combinatorial isolation lemmas

Watermarking graph partitioning solutions

Hardware metering

Technical visualizations in VLSI design: visualization

Using texture mapping with mipmapping to render a VLSI layout

Web-based algorithm animation

Speeding up control-dominated applications through microarchitectural customizations in embedded processors

Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip

Dynamic voltage scaling and power management for portable systems

Chaff: engineering an efficient SAT solver

Dynamic detection and removal of inactive clauses in SAT with application in image computation

SATIRE: a new incremental satisfiability engine

A framework for low complexitgy static learning

Fast power/ground network optimization based on equivalent circuit modeling

An interconnect energy model considering coupling effects

Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods

Using conduction modes basis functions for efficient electromagnetic anaysis of on-chip and off-chip interconnect

Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs

VHDL-based design and design methodology for reusable high performance direct digital requency synthesizers

Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit symmetric block ciphers

MetaCores: design and optimization techniques

Is nanometer design under control? (panel session)

A hardware/software co-design flow and IP library based on simulink

System-level power/performance analysis for embedded systems design

High-level software energy macro-modeling

Model checking of S3C2400X industrial embedded SOC product

Semi-formal test generation with genevieve

A transaction-based unified simulation/emulation architecture for functional verification

Integrated high-level synthesis and power-net routing for digital design under switching noise constraints

Integrating scheduling and physical design into a coherent compilation cycle for reconfigurable computing architectures

Statistical design space exploration for application-specific unit synthesis

Static schedluing of multiple asynchronous domains for functional verification

Functional correlation analysis in crosstalk induced critical paths identification

An advanced timing characterization method using mode dependecy

Fast statistical timing analysis by probabilistic event propagation

Addressing the system-on-a-chip interconnect woes through communication-based design

Micronetwork-based integration for SOCs: 673

On-chip communication architecture for OC-768 network processors

Route packets, not wires: on-chip inteconnection networks

Dynamic management of scratch-pad memory space

Clustered VLIW architecture with predicated switching

High-quality operation binding for clustered VLIW datapaths

Fast bit-true simulation

Timing analysis with crosstalk as fixpoints on complete lattice

Driver modeling and alignment for worst-case delay noise

False coupling interactions in static timing analysis

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique

Input space adaptive design: a high-level methodology for energy and performance optimization

A\$^{\mbox{\huge\bf 2}}\$BC: adaptive address bus coding for low power deep sub-micron designs

Coupling-driven bus design for low-power application-specific systems

Modeling and minimization of interconnect energy dissipation in nanometer technologies

A true single-phase 8-bit adiabatic multiplier

TCG: a transitive closure graph-based representation for non-slicing floorplans

Floorplanning with abutment constraints and L-shpaed/T-shaped blocks baed on corner block list

Improved cut sequences for partitioning based placement

Timing driven placement using physical net constraints

From architecture to layout: partitioned memory synthesis for embedded systems-on-chip

What drives EDA innovaiton? (panel session)

Built-in self-test for signal integrity

Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed RLC interconnects

Modeling and analysis of differential signaling for minimizing inductive cross-talk

Automated pipeline design

A new verification methodology for complex pipeline behavior

Pre-silicon verification of the Alpha 21364 microprocessor error handling system

Energy efficient fixed-priority scheduling for real-time systems on variable voltage processors

Dynamic power management in a mobile multimedia system with guaranteed quality-of-service

Power-aware scheduling under timing constraints for mission-critical embedded systems

Exploring SOI device structures and interconnect architecures for 3-dimensional integration

Two-dimensional position deteciton system with MEMS accelerometer for MOUSE applications

Mismatch analysis and direct yield optimization by specwise linearization and feasibility-guided search

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2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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