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A tag-based dynamic memory map architecture in VHDL
| Content Provider | ACM Digital Library |
|---|---|
| Author | Visser, M. Naudé, J. P. |
| Abstract | This paper presents the architecture of a small, generic and proven dynamic memory map (DMM) firmware solution for VHDL developers. The dynamic memory map allows digital designers to construct dynamic memory map structures, where registers can be added or removed on a function level at design time without knowledge of the memory layout of the overall system in which the function will be used. Registers are grouped on a function level and each function can be identified and located in the map through tags containing unique function identifiers (IDs), assigned on a system level. The structure is automatically parsed and initialized at runtime. After initialization the DMM routes register requests to the correct location in the memory map using only the function ID and the address offset within the function. The DMM uses various timeout mechanisms to ensure that it always remains operational, even when a function does not perform as expected. An architectural overview is presented along with operational details, different interrogation techniques, comparison with other popular interconnects and cross-vendor resource utilization tables. |
| Starting Page | 1 |
| Ending Page | 6 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781450316453 |
| DOI | 10.1145/2451636.2451638 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2012-09-04 |
| Publisher Place | New York |
| Access Restriction | Subscribed |
| Subject Keyword | Vhdl Design reuse Register access Firmware interconnect Memory mapping |
| Content Type | Text |
| Resource Type | Article |
