NDLI: Predicting the worst-case voltage violation in a 3D power network

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Predicting the worst-case voltage violation in a 3D power network

Content Provider	ACM Digital Library
Author	Engin, A. Ege Hu, Xiang Zhang, Wanping Yu, Wenjian Shayan, Amirali Cheng, Chung-Kuan
Abstract	This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering leakage current. We first describe the 3D Power Distribution Network (PDN) structure which includes on-chip inductance and through-silicon-vias (TSV). The analysis flow using a superposition technique will be introduced later on. Then, we propose a general model to identify the worst-case gating pattern and the maximum variation area with arbitrary leakage current. For low power wireless chips, we introduce another simplified model, which treats the leakage to be a DC current. We formulate these two models with integer linear programming (ILP). The ILP based method is significantly faster than a conventional method based on enumeration. The experimental results also show that the noise contributed by leakage current is not negligible.
Starting Page	93
Ending Page	98
Page Count	6
File Format	PDF
ISBN	9781605585765
DOI	10.1145/1572471.1572487
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-07-26
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Leakage Clock gating Integer linear programming Power networks Worst case violation prediction
Content Type	Text
Resource Type	Article

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