NDLI: Challenges and Opportunities with Place and Route of Modern FPGA Designs

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Challenges and Opportunities with Place and Route of Modern FPGA Designs

Content Provider	ACM Digital Library
Author	Nijssen, Raymond
Abstract	In the last decade place and route algorithms used for large high performance FPGA designs have been successfully adapted from those used in ASIC design flows. All major FPGA tool sets now use advanced analytical global placement algorithms with sophisticated cell clustering. Thanks to this, fast runtimes and predictable performance on designs with millions of placeable objects empower designers to quickly and often evaluate their decisions. Fast design flow turn-around times and predictability are of tremendous value to help designers improve timing closure problems in their designs, and accommodate them to floorplanning constraints and congestion bottlenecks. Although many P&R related aspects are common between ASIC and FPGA technologies, many are unique to FPGAs. For example, the many tight, rigid constraints, as well as aggressive runtime requirements and the heterogeneity of the problems. As these unique challenges have received relatively little coverage in literature this presentation focuses on the entailing opportunities. In particular, unlike ASICs in which different types of cell instances can be moved between and within rows freely, FPGAs have discrete, fixed heterogeneous resource locations onto which the user design must be fitted: a flip-flop instance in the user netlist can only be placed onto a flip-flop site of the FPGA fabric. Carry chains in FPGA fabrics are very fast, but run only vertically, typically only in one direction. And the routing fabric of an FPGA must impose countless routing restrictions, like one-way routing and input sharing, without which the size of the chip would become prohibitively large. These essential restrictions must be well understood and taken into account in algorithms targeting FPGAs. In its first part, this presentation will cover several examples of such aspects and will suggest approaches. The second part covers incremental compilation, various forms of parallel processing are other must-have features for a competitive FPGA P&R flow. Such techniques present challenges that demand a more algorithmical approach to take these to the next level. Third, modern FPGAs have evolved far from the original textbook LUT-flop logic building blocks. They feature a hybrid between much more complex logic blocks and a rich variety of ASIC blocks implementing various commonly used IP like PCIe controllers, feature-rich IOs and dedicated function blocks in the FPGA core. FPGA P&R flows offering a more seamless integration between these environments must also automate the process of configuring such diverse components and all the connections related to it. Finally, next generations of FPGAs and their EDA systems are facing peripheral interfaces whose bandwidths increase very rapidly while the processing logic's propagation delays are not expected to reduce significantly in upcoming fabrication technology nodes. Several existing and new techniques to deal with this widening discrepancy will need to be applied more aggressively, calling for new features in FPGA P&R algorithms in the near future.
Starting Page	57
Ending Page	57
Page Count	1
File Format	PDF
ISBN	9781450340397
DOI	10.1145/2872334.2872336
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-04-03
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Placement algorithms Fpga Routing algorithms
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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