NDLI: Standard cell placement using simulated sintering

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SSIM: a software levelized compiled-code simulator

COSMOS: a compiled simulator for MOS circuits

A fast signature simulation tool for built-in self-testing circuits

An improved systematic method for constructing systolic arrays from algorithms

Predicting area-time tradeoffs for pipelined design

A prototype framework for knowledge-based analog circuit synthesis

An automatic rectilinear partitioning procedure for standard cells

Standard cell placement using simulated sintering

ESP: a new standard cell placement package using simulated evolution

Requirements for a practical software engineering environment

The making of VIVID: a software engineering perspective

A case study in silicon compilation software engineering, HVDEV high voltage device layout generator

A vector hardware accelerator with circuit simulation emphasis

A hardware switch level simulator for large MOS circuits

Architecture and design of the MARS hardware accelerator

Circuit simulation on the connection machine

Aesop: a tool for automated transistor sizing

Transistor sizing in CMOS circuits

Delay optimization of combinational static CMOS logic

Reflections of high speed signals analyzed as a delay in timing for clocked logic

Geometrical compaction in one dimension for channel routing

A three-layer gridless channel router with compaction

Routing L-shaped channels in nonslicing-structure placement

Via minimization for gridless layouts

An overview of logic synthesis systems

Realistic fault modeling for VLSI testing

Demand driven simulation: BACKSIM

Faster architectural simulation through parallelism

Force-directed scheduling in automatic data path synthesis

Knowledge based control in micro-architecture design

REAL: a program for REgister ALlocation

A practical moat router

An automated design of minimum-area IC power/ground nets

Abstract routing of logic networks for custom module generation

Accelerated transition fault simulation

On accuracy of switch-level modeling of bridging faults in complex gates

Integrating design information for IC diagnosis

Switch directed dynamic causal networks—a paradigm for electronic system diagnosis

Functional verification of MOS circuits

On the verification of sequential machines at differing levels of abstraction

Application of term rewriting techniques to hardware design verification

Logic verification algorithms and their parallel implementation

Generating incremental VLSI compaction spacing constraints

Nutcracker: an efficient and intelligent channel spacer

Improving virtual-grid compaction through grouping

KAHLUA: a hierarchical circuit disassembler

Benchmarks for cell-based layout systems

VALKYRIE: a validation subsystem of a version server for computer-aided design data

Querying part hierarchies: a knowledge-based approach

An object-oriented approach to data management: why design databases need it

DAGON: technology binding and local optimization by DAG matching

Finding the optimal variable ordering for binary decision diagrams

Mesh arrays and LOGICIAN: a tool for their efficient generation

Strip layout: a new layout methodology for standard circuit modules

The ALGIC silicon compiler system: implementation, design experience and results

A dynamic and efficient representation of building-block layout

BIST-PLA: a built-in self-test design of large programmable logic arrays

On computing optimized input probabilities for random tests

VLSI circuit testing using and adaptive optimization model

Circular self-test path: a low-cost BIST technique

PHRAN-SPAN: a natural language interface for system specifications

TED: a graphical technology description editor

“?”: a context-sensitive help system based on hypertext

VISION: VHDL induced schematic imaging on net-lists

An intelligent compiler subsystem for a silicon compiler

Fast, small, and static combinatorial CMOS circuits

LCS—a leaf cell synthesizer employing formal deduction techniques

A design rule independent cell compiler

An interface between VHDL and EDIF

Tutorial: reading and reviewing the common schema for electrical design and analysis

The IBM VHDL design system

Where VHDL fits within the CAD environment

A hierarchical approach test vector generation

A topological search algorithm for ATPG

Benchmark runs of the subscripted D-Algorithm with observation path mergers on the Brglez-Fujiwara circuits

An overview of the Penn State design system

TRIP: an automated technology mapping system

ASTA: LSI design management system

Array optimization for VLSI synthesis

Layout optimization of CMOS functional cells

Automated layout generation using gate matrix approach

The design automation standards environment

Design automation standards need integration

Design automation standards—perspectives from a down-the-road end user

Needed: a meta-language for evaluating the expressiveness of EDIF, IGES, VHDL and other representation mechanisms

HPEX: a hierarchical parasitic circuit extractor

RED: resistance extraction for digital simulation

Function search from behavioral description of a digital system

The implementation of a state machine compiler

Boolean comparison by simulation

Statistics for parallelism and abstraction level in digital simulation

A conceptual framework for designing ASIC hardware

CASE: an integrated design environment for algorithm-driven architectures

A parallel PLA minimization program

Improving a PLA area by pull-up transistor folding

PALMINI—fast Boolean minimizer for personal computers

On yield consideration for the design of redundant programmable logic arrays

Routing with a scanning window-8Ma unified approach

A “gridless” variable-width channel router for marco cell design

General purpose router

A path selection global touter

A new compaction scheme based on compression ridges

Hierarchical design based on a calculus of nets

An application of exploratory data analysis techniques to floorplan design

PLAY: pattern-based symbolic cell layout: Part I: transistor placement

PAMS: an expert system for parameterized module synthesis

LES: a layout expert system

An expert system application in semicustom VLSI design

Design and algorithms for parallel testing of random access and content addressable memories

A dynamic programming approach to the test point insertion problem

A parts selection expert system to increase manufacturability

Knowledge based approach for the verification of CAD database generated by an automated schematic capture system

A new interactive supply/demand router with rip-up capability for printed circuit boards

Fast printed circuit board routing

Heuristic acceleration of force-directed placement

EASE: a design support environment for the HDDL ELLA

CHESHIRE: an object-oriented integration of VLSI CAD tools

STEM: an IC design environment based on the Smalltalk model-view-controller construct

Rational for and organization of the engineering information system program

A discrete heuristics approach to predictive evaluation of semi-custom IC layouts

A rule-based placement system for printed wiring boards

A rule-based circuit representation for automated CMOS design and verification

A high performance routing engine

A hardware accelerator for maze routing

Performance of a parallel algorithm for standard cell placement on the Intel hypercube

A preliminary investigation into parallel routing on a hypercube computer

Functional abstraction from structure in VLSI simulation models

Optimal layout to avoid CMOS stuck-open faults

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