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| Content Provider | ACM Digital Library |
|---|---|
| Author | Selvakkumaran, Navaratnasothie Raje, Salil Karypis, George Ranjan, Abhishek |
| Abstract | As the chip densities increase, the modern FPGAs contain large capacity and increasingly provide heterogeneous units such as multipliers, processor/DSP cores, RAM-blocks etc, for efficient execution of crucial functions of the design. The hypergraph partitioning algorithms are generally used as a divide-and-conquer strategy, during synthesis and placement. The partitioning algorithms for designs with heterogeneous resources, need to not only minimize the cut, but also balance the individual types of resources. Unfortunately, the state-of-the-art multilevel hypergraph partitioning algorithms (hMetis,MLPart), are not capable of distinguishing the types of cells. To overcome this problem, we developed a new set of multilevel hypergraph partitioning algorithms, that are aware of multiple resources, and are guaranteed to balance the utilization of different resources. By evaluating these algorithms on large benchmarks, we found that it is possible to achieve such feasible partitions, while incurring only a slightly higher cut (3.3%-5.7%) compared to infeasible partitions generated by hMetis. |
| Starting Page | 253 |
| Ending Page | 253 |
| Page Count | 1 |
| ISBN | 1581138296 |
| DOI | 10.1145/968280.968339 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2004-02-22 |
| Publisher Place | New York |
| Access Restriction | Subscribed |
| Content Type | Text |
| Resource Type | Article |
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