NDLI: OD3P: On-Demand Page Paired PCM

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Verification of Non-Mainline Functions in Todays Processor Chips

Validation of SoC Firmware-Hardware Flows: Challenges and Solution Directions

Architecting Dynamic Power Management to be Formally Verifiable

On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective

Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs

On Timing Closure: Buffer Insertion for Hold-Violation Removal

Post-Routing Latch Optimization for Timing Closure

Contactless Stacked-die Testing for Pre-bond Interposers

Leveraging pre-silicon data to diagnose out-of-specification failures in mixed-signal circuits

One-Shot Calibration of RF Circuits Based on Non-Intrusive Sensors

On Using Implied Values in EDT-based Test Compression

ASER: Adaptive Soft Error Resilience for Reliability-Heterogeneous Processors in the Dark Silicon Era

Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors

An Efficient Real Time Fault Detection and Tolerance Framework Validated on the Intel SCC Processor

Multi-Objective Local-Search Optimization using Reliability Importance Measuring

eButton: A Wearable Computer for Health Monitoring and Personal Assistance

Ultra-Low Power Design of Wearable Cardiac Monitoring Systems

Exploiting Shaper Context to Improve Performance Bounds of Ethernet AVB Networks

An Efficient Wire Routing and Wire Sizing Algorithm for Weight Minimization of Automotive Systems

Schedule Integration Framework for Time-Triggered Automotive Architectures

Aspect-oriented Modeling of Attacks in Automotive Cyber-Physical Systems

Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex Hardware

Translation Validation for Stateflow to C

Advanced Soft-Error-Rate (SER) Estimation with Striking-Time and Multi-Cycle Effects

LiVe: Timely Error Detection in Light-Lockstep Safety Critical Systems

BEOL Scaling Limits and Next Generation Technology Prospects

On the Design of Reliable 3D-ICs Considering Charged Device Model ESD Events During Die Stacking

Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling

BMF-BD: Bayesian Model Fusion on Bernoulli Distribution for Efficient Yield Estimation of Integrated Circuits

Remembrance of Transistors Past: Compact Model Parameter Extraction Using Bayesian Inference and Incomplete New Measurements

Static Mapping of Mixed-Critical Applications for Fault-Tolerant MPSoCs

GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems

FALCON: A Framework for HierarchicAL Computation of Metrics for CompONent-Based Parameterized SoCs

Ontology-guided Conceptual Analysis of Design Specifications

State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System

SLC-enabled Wear Leveling for MLC PCM Considering Process Variation

Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture

Leveraging Data Lifetime for Energy-Aware Last Level Non-Volatile SRAM Caches using Redundant Store Elimination

Computation Offloading by Using Timing Unreliable Components in Real-Time Systems

Integrated CPU-GPU Power Management for 3D Mobile Games

Content-centric Display Energy Management for Mobile Devices

Catch Your Attention: Quality-retaining Power Saving on Mobile OLED Displays

A Secure but still Safe and Low Cost Automotive Communication Technique

Typical Worst Case Response-Time Analysis and its Use in Automotive Network Design

Powertrain Co-Simulation using AUTOSAR and the Functional Mockup Interface standard

Monitoring Reliability in Embedded Processors - A Multi-layer View

Multi-Layer Dependability: From Microarchitecture to Application Level

Multi-Layer Memory Resiliency

Workload- and Instruction-Aware Timing Analysis: The missing Link between Technology and System-level Resilience

Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process

Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout

MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction

Layout Decomposition for Quadruple Patterning Lithography and Beyond

Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification

Directed Self-Assembly (DSA) Template Pattern Verification

Post-Silicon Validation of the IBM POWER8 Processor

Coverage Learned Targeted Validation for Incremental HW Changes

Verification of Transactional Memory in POWER8

A SystemC Virtual Prototyping based Methodology for Multi-Standard SoC Functional Verification

Balancing Scalability and Uniformity in SAT Witness Generator

Code Coverage of Assertions Using RTL Source Code Analysis

Power-Performance Study of Block-Level Monolithic 3D-ICs Considering Inter-Tier Performance Variations

A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability

OD3P: On-Demand Page Paired PCM

Modeling and Analysis of Domain Wall Dynamics for Robust and Low-Power Embedded Memory

Simultaneous Sizing, Reference Voltage and Clamp Voltage Biasing for Robustness, Self-Calibration and Testability of STTRAM Arrays

Computer-Aided Design of Machine Learning Algorithm: Training Fixed-Point Classifier for On-Chip Low-Power Implementation

Sense-making from Distributed and Mobile Sensing Data: A Middleware Perspective

Resource Efficient Mobile Communications for Crowd-Sensing

Demystifying Energy Usage in Smartphones

Metasynthesis for Designing Automotive SoCs

Design Methods for Augmented Reality In-Vehicle Infotainment Systems

Computing with Hybrid CMOS/STO Circuits

Neuro Inspired Computing with Coupled Relaxation Oscillators

Reliability-aware Register Binding for Control-Flow Intensive Designs

Flushing-Enabled Loop Pipelining for High-Level Synthesis

An Optimal Microarchitecture for Stencil Computation Acceleration Based on Non-Uniform Partitioning of Data Reuse Buffers

CGPA: Coarse-Grained Pipelined Accelerators

Early-Stage Power Grid Design: Extraction, Modeling and Optimization

Physics-based Electromigration Assessment for Power Grid Networks

MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks

REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage

On Trading Wear-leveling with Heal-leveling

dTune: Leveraging Reliable Code Generation for Adaptive Dependability Tuning under Process Variation and Aging-Induced Effects

User-Centric Energy-Efficient Scheduling on Multi-Core Mobile Devices

Sufficient Temporal Independence and Improved Interrupt Latencies in a Real-Time Hypervisor

Low-cost On-Chip Structures for Combating Die and IC Recycling

CACI: Dynamic Current Analysis Towards Robust Recycled Chip Identification

A Highly Flexible Ring Oscillator PUF

Reverse Engineering and Prevention Techniques for Physical Unclonable Functions Using Side Channels

An Automobile Detection Algorithm Development for Automated Emergency Braking System

A Cost Efficient Online Algorithm for Automotive Idling Reduction

Scalable Co-Simulation of Functional Models With Accurate Event Exchange

Design and Implementation of a Dynamic Component Model for Federated AUTOSAR Systems

Automated Specification and Verification of Functional Safety in Heavy-Vehicles: the VeriSpec Approach

Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures

ApproxIt: An Approximate Computing Framework for Iterative Methods

Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold Designs

Low Power GPGPU Computation with Imprecise Hardware

Power / Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches

SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems

Fault-tolerant Routing for On-chip Network Without Using Virtual Channels

VIX: Virtual Input Crossbar for Efficient Switch Allocation

Disease Diagnosis-on-a-Chip: Large Scale Networks-on-Chip based Multicore Platform for Protein Folding Analysis

CAP: Communication Aware Programming

Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM

Branch-Aware Loop Mapping on CGRAs

Reduction Operator for Wide-SIMDs Reconsidered

PUFatt: Embedded Platform Attestation Based on Novel Processor-Based PUFs

Beyond ECDSA and RSA: Lattice-based Digital Signatures on Constrained Devices

Software Only, Extremely Compact, Keccak-based Secure PRNG on ARM Cortex-M

Ultra Low-Power implementation of ECC on the ARM Cortex-M0+

Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges

Steep Slope Devices: Enabling New Architectural Paradigms

Approximate property checking of mixed-signal circuits

A Rigorous Graphical Technique for Predicting Sub-harmonic Injection Locking in LC Oscillators

An Efficient Two-level DC Operating Points Finder for Transistor Circuits

A Time-Unrolling Method to Compute Sensitivity of Dynamic Systems

Selective Inversion of Inductance Matrix for Large-Scale Sparse RLC Simulation

Probabilistic Bug Localization via Statistical Inference based on Partially Observed Data

ePlace: Electrostatics Based Placement Using Nesterov's Method

Density-aware Detailed Placement with Instant Legalization

POLAR 2.0: An Effective Routability-Driven Placer

Routability-Driven Blockage-Aware Macro Placement

Row Based Dual-VDD Island Generation and Placement

Walking Pads: Managing C4 Placement for Transient Voltage Noise Minimization

Symbolic Analysis of Dataflow Applications Mapped onto Shared Heterogeneous Resources

A Design Methodology for Compositional High-Level Synthesis of Communication-Centric SoCs

DAPs: Dynamic Adjustment and Partial Sampling for Multithreaded/Multicore Simulation

Area-Efficient Event Stream Ordering for Runtime Observability of Embedded Systems

On the Scheduling of Fault-Tolerant Mixed-Criticality Systems

An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video Processing

Hardware-Assisted Fine-Grained Control-Flow Integrity: Towards Efficient Protection of Embedded Systems Against Software Exploitation

Using a High-Level Test Generation Expert System for Testing In-Car Networks

Statistical Battery Models and Variation-Aware Battery Management

Battery Management and Application for Energy-Efficient Buildings

System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs

Hardware-in-the-loop Simulation for CPU/GPU Heterogeneous Platforms

Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes

A Swap-based Cache Set Index Scheme to Leverage both Superpage and Page Coloring Optimizations

An Efficient Bi-criteria Flow Channel Routing Algorithm For Flow-based Microfluidic Biochips

Exact One-pass Synthesis of Digital Microfluidic Biochips

Practical Functional and Washing Droplet Routing for Cross-Contamination Avoidance in Digital Microfluidic Biochips

Demand-Driven Mixture Preparation and Droplet Streaming using Digital Microfluidic Biochips

EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs

Retention Trimming for Wear Reduction of Flash Memory Storage Systems

Space-Efficient Multiversion Index Scheme for PCM-based Embedded Database Systems

Deterministic Crash Recovery for NAND Flash Based Storage Systems

Scalable Certification Framework for Behavioral Synthesis Front-End

Parallel Hierarchical Reachability Analysis for Analog Verification

Automatic Verification of Floating Point Units

Equivalence Verification of Large Galois Field Arithmetic Circuits using Word-Level Abstraction via Gröbner Bases

Circuit Camouflage Integration for Hardware IP Protection

FPGA Security: From Features to Capabilities to Trusted Systems

Hardware Trojan Detection through Golden Chip-Free Statistical Side-Channel Fingerprinting

Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack

High-Level Synthesis for Run-Time Hardware Trojan Detection and Recovery

Fort-NoCs: Mitigating the Threat of a Compromised NoC

Data Mining In EDA - Basic Principles, Promises, and Constraints

NoC-Sprinting: Interconnect for Fine-Grained Sprinting in the Dark Silicon Era

darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon

Power-Aware NoCs through Routing and Topology Reconfiguration

Quality-of-Service for a High-Radix Switch

Enabling Efficient Analog Synthesis by Coupling Sparse Regression and Polynomial Optimization

Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC

Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 12-bit SAR ADC Design Case

An HDL-Based System Design Methodology for Multistandard RF SoC's

Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUs

On the Simulation of NBTI-Induced Performance Degradation Considering Arbitrary Temperature and Voltage Variations

Reinforcement Learning-Based Inter- and Intra-Application Thermal Optimization for Lifetime Improvement of Multicore Systems

Modeling and Experimental Demonstration of Accelerated Self-Healing Techniques

Designing Stealthy Trojans with Sequential Logic: A Stream Cipher Case Study

FIGHT-Metric: Functional Identification of Gate-Level Hardware Trustworthiness

Advanced Techniques for Designing Stealthy Hardware Trojans

A Red Team/Blue Team Assessment of Functional Analysis Methods for Malicious Circuit Identification

A Side-channel Analysis Resistant Reconfigurable Cryptographic Coprocessor Supporting Multiple Block Cipher Algorithms

Tile Before Multiplication: An Efficient Strategy to Optimize DSP Multiplier for Accelerating Prime Field ECC for NIST Curves

Secure Memristor-based Main Memory

TI-TRNG: Technology Independent True Random Number Generator

Accelerator-Rich Architectures: Opportunities and Progresses

Exploring the Heterogeneous Design Space for both Performance and Reliability

Enabling Dynamic Heterogeneity Through Core-on-Core Stacking

Power management through DVFS and dynamic body biasing in FD-SOI circuits

Thermal Implications of On-Chip Voltage Regulation: Upcoming Challenges and Possible Solutions

The EDA Challenges in the Dark Silicon Era: Temperature, Reliability, and Variability Perspectives

Power-Aware Deployment and Control of Forced-Convection and Thermoelectric Coolers

Thermal-Sustainable Power Budgeting for Dynamic Threading

ClusRed: Clustering and Network Reduction Based Probabilistic Optimal Power Flow Analysis for Large-Scale Smart Grids

TACUE: A Timing-Aware Cuts Enumeration Algorithm for Parallel Synthesis

Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs

Functional ECO Using Metal-Configurable Gate-Array Spare Cells

Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits

Parallel FPGA Routing based on the Operator Formulation

Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization

Energy-Efficient GPGPU Architectures via Collaborative Compilation and Memristive Memory-Based Computing

Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory

An Efficient STT-RAM Last Level Cache Architecture for GPUs

Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems

Variation Aware Cache Partitioning for Multithreaded Programs

MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis

Radiation-Induced Soft Error Analysis of SRAMs in SOI FinFET Technology: A Device to Circuit Approach

Robust and In-Situ Self-Testing Technique for Monitoring Device Aging Effects in Pipeline Circuits

BTI-Induced Aging under Random Stress Waveforms: Modeling, Simulation and Silicon Validation

A New Asynchronous Pipeline Template for Power and Performance Optimization

C-Mine: Data Mining of Logic Common Cases for Low Power Synthesis of Better-Than-Worst-Case Designs

Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs

Hardware/Software Co-Design of Elliptic-Curve Cryptography for Resource-Constrained Applications

Techniques for Foundry Identification

QMS: Evaluating the Side-Channel Resistance of Masked Software from Source Code

A Multiple Equivalent Execution Trace Approach to Secure Cryptographic Embedded Software

System-Level Security for Network Processors with Hardware Monitors

Protecting SRAM-based FPGAs Against Multiple Bit Upsets Using Erasure Codes

The First EDA MOOC: Teaching Design Automation to Planet Earth

OD3P: On-Demand Page Paired PCM

Content Provider	ACM Digital Library
Author	Asadinia, Marjan Arjomand, Mohammad Sarbazi-Azad, Hamid
Abstract	With current memory scalability challenges, Phase Change Memory (PCM) is viewed as an attractive replacement to DRAM. The preliminary concern for PCM applicability is its limited write endurance that is highly affected by process variation in nanometer regime. This increases the variation in cell lifetime resulting in early and sudden reduction in main memory capacity due to wear-out of few cells. When some memory pages reach their endurance limits, other pages may be far from their limits even when using a perfect wear-leveling. Recent studies have proposed redirection or correction schemes to alleviate this problem, but all suffer from poor throughput or latency. On contrary, we present On-Demand Page Paired PCM (OD3P), a technique that mitigates the problem of fast failure of pages by redirecting them onto other healthy pages, leading to gradual capacity degradation. Compared to a state-of-the-art error correction scheme for PCM, our experiments indicated that OD3P can improve PCM time-to-failure and system performance (IPC) by 12% and 14%, respectively, under multi-threaded and multi-programmed workloads.
Starting Page	1
Ending Page	6
Page Count	6
File Format	PDF
ISBN	9781450327305
DOI	10.1145/2593069.2593166
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-06-01
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Lifetime Page pairing
Content Type	Text
Resource Type	Article

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