NDLI: Dynamic Memory Pressure Aware Ballooning

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Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems

A Data Centric Perspective on Memory Placement

Opportunities to Upgrade Main Memory

Implications of Memory Interference for Composed HPC Applications

Architecture Exploration for Data Intensive Applications

HpMC: An Energy-aware Management System of Multi-level Memory Architectures

Anatomy of GPU Memory System for Multi-Application Execution

Energy Efficient Scale-In Clusters with In-Storage Processing for Big-Data Analytics

Near Data Processing: Impact and Optimization of 3D Memory System Architecture on the Uncore

The Semantic Gap Between Software and the Memory System

E-ECC: Low Power Erasure and Error Correction Schemes for Increasing Reliability of Commodity DRAM Systems

Software Techniques for Scratchpad Memory Management

MEMST: Cloning Memory Behavior using Stochastic Traces

Bringing Modern Hierarchical Memory Systems Into Focus: A study of architecture and workload factors on system performance

Inefficiencies in the Cache Hierarchy: A Sensitivity Study of Cacheline Size with Mobile Workloads

NCAM: Near-Data Processing for Nearest Neighbor Search

Opportunities and Challenges of Performing Vector Operations inside the DRAM

MMC: a Many-core Memory Connection Model

Writing without Disturb on Phase Change Memories by Integrating Coding and Layout Design

Dynamic Memory Pressure Aware Ballooning

Modeling Data Movement in the Memory Hierarchy in HPC Systems

The Potential and Perils of Multi-Level Memory

Herniated Hash Tables: Exploiting Multi-Level Phase Change Memory for In-Place Data Expansion

Understanding Energy Aspects of Processing-near-Memory for HPC Workloads

SIMT-based Logic Layers for Stacked DRAM Architectures: A Prototype

High Performance Computing Co-Design Strategies

Achieving Yield, Density and Performance Effective DRAM at Extreme Technology Sizes

Shared Last-Level Caches and The Case for Longer Timeslices

Rethinking Design Metrics for Datacenter DRAM

k-Means Clustering on Two-Level Memory Systems

Instruction Offloading with HMC 2.0 Standard: A Case Study for Graph Traversals

Near memory data structure rearrangement

Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC?

Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs

S-L1: A Software-based GPU L1 Cache that Outperforms the Hardware L1 for Data Processing Applications

Towards Workload-Aware Page Cache Replacement Policies for Hybrid Memories

Dynamic Memory Pressure Aware Ballooning

Content Provider	ACM Digital Library
Author	Kim, Jinchun Gratz, Paul V. Reddy, A. L. Narasimha Fedorov, Viacheslav
Abstract	Hardware virtualization is a major component of large scale server and data center deployments due to their facilitation of server consolidation and scalability. Virtualization, however, comes at a high cost in terms of system main memory utilization. Current virtual machine (VM) memory management solutions impose a high performance penalty and are oblivious to the operating regime of the system. Therefore, there is a great need for low-impact VM memory management techniques which are aware of and reactive to current system state, to drive down the overheads of virtualization. We observe that the host machine operates under different memory pressure regimes, as the memory demand from guest VMs changes dynamically at runtime. Adapting to this runtime system state is critical to reduce the performance cost of VM memory management. In this paper, we propose a novel dynamic memory management policy called Memory Pressure Aware (MPA) ballooning. MPA ballooning dynamically allocates memory resources to each VM based on the current memory pressure regime. Moreover, MPA ballooning proactively reacts and adapts to sudden changes in memory demand from guest VMs. MPA ballooning requires neither additional hardware support, nor incurs extra minor page faults in its memory pressure estimation. We show that MPA ballooning provides an 13.2% geomean speed-up versus the current ballooning techniques across a set of application mixes running in guest VMs; often yielding performance nearly identical to that of a non-memory constrained system.
Starting Page	103
Ending Page	112
Page Count	10
File Format	PDF
ISBN	9781450336048
DOI	10.1145/2818950.2818967
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-10-05
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Memory management Virtualization Operating system
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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