NDLI: Focusing processor policies via critical-path prediction

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Program Chair's Message

Conference Organization

Reviewers

Execution-based prediction using speculative slices

Opening Remarks

Speculative precomputation: long-range prefetching of delinquent loads

Dynamically allocating processor resources between nearby and distant ILP

Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors

Data prefetching by dependence graph precomputation

Concurrency, latency, or system overhead: which has the largest impact on uniprocessor DRAM-system performance?

Focusing processor policies via critical-path prediction

Automated design of finite state machine predictors for customized processors

Better exploration of region-level value locality with integrated computation reuse and value prediction

CryptoManiac: a fast flexible architecture for secure communication

QoS provisioning in clusters: an investigation of Router and NIC design

Locality vs. criticality

Dead-block prediction & dead-block correlating prefetchers

Code layout optimizations for transaction processing workloads

Exploring and exploiting wire-level pipelining in emerging technologies

NanoFabrics: spatial computing using molecular electronics

A simple method for extracting models for protocol code

Removing architectural bottlenecks to the scalability of speculative parallelization

Power and energy reduction via pipeline balancing

Energy-effective issue logic

Cache decay: exploiting generational behavior to reduce cache leakage power

Variability in the execution of multimedia applications and implications for architecture

Measuring Experimental Error in Microprocessor Simulation

Rapid profiling via stratified sampling

Author Index

Focusing processor policies via critical-path prediction

Content Provider	ACM Digital Library
Author	Fields, Brian Rubin, Shai Bodík, Rastislav
Abstract	Although some instructions hurt performance more than others, current processors typically apply scheduling and speculation as if each instruction was equally costly. Instruction cost can be naturally expressed through the critical path: if we could predict it at run-time, egalitarian policies could be replaced with cost-sensitive strategies that will grow increasingly effective as processors become more parallel.This paper introduces a hardware predictor of instruction criticality and uses it to improve performance. The predictor is both effective and simple in its hardware implementation. The effectiveness at improving performance stems from using a dependence-graph model of the microarchitectural critical path that identifies execution bottlenecks by incorporating both data and machine-specific dependences. The simplicity stems from a token-passing algorithm that computes the critical path without actually building the dependence graph.By focusing processor policies on critical instructions, our predictor enables a large class of optimizations. It can (i) give priority to critical instructions for scarce resources (functional units, ports, predictor entries); and (ii) suppress speculation on non-critical instructions, thus reducing “useless” misspeculations. We present two case studies that illustrate the potential of the two types of optimization, we show that (i) critical-path-based dynamic instruction scheduling and steering in a clustered architecture improves performance by as much as 21% (10% on average); and (ii) focusing value prediction only on critical instructions improves performance by as much as 5%, due to removing nearly half of the misspeculations.
Starting Page	74
Ending Page	85
Page Count	12
File Format	PDF
ISBN	0769511627
DOI	10.1145/379240.379253
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2001-06-01
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Focusing Processor Policies via Critical-Path Prediction (2001)

Focusing processor policies via critical-path prediction

Focusing processor policies via critical-path prediction

Abstract Focusing Processor Policies via Critical-Path Prediction

Focusing Processor Policies via Critical-Path Prediction (2001)

Focusing processor policies via critical-path prediction (2001)

Focusing processor policies via critical-path prediction (2001)

Focusing processor policies via critical-path prediction (2001)

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Focusing processor policies via critical-path prediction

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