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  1. Proceedings of the Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings. (MEMOCODE '06)
  2. Session II: Rule-based HW Design
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Proceedings. Fourth ACM & IEEE International Conference on Formal Methods and Models for Co-Design. (MEMOCODE'06) (IEEE Cat. No. 06EX1398)
Copyright
Message from the Chairs
Organizers and Program Committee Members
Table of Contents
Keynote Talk I
Games for formal design and verification of reactive systems
Session I: Model Checking
Analyzing tabular requirements specifications using infinite state model checking
Mixed symbolic representations for model checking software programs
Component-based hardware/software co-verification
Session II: Rule-based HW Design
A rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-design
Low-power hardware synthesis from TRS-based specifications
802.11a transmitter: a case study in microarchitectural exploration
Session III: HW Verification
Automatic decomposition for sequential equivalence checking of system level and RTL descriptions
A verified development of hardware using CSP/spl par/B
Panel I: Nano-Computing: Do we need New Formal Approaches to Co-Design?
Panel: Nano-computing - do we need new formal approaches ?
Keynote Talk II
Scalable program analysis using Boolean satisfiability
Session IV: Transaction-level Modeling
Execution semantics and formalisms for multi-abstraction TLM assertions
A methodology for abstracting RTL designs into TL descriptions
Using Reo for formal specification and verification of system designs
Panel II: Programming Models and Languages for SOC-Implemented Architectures
Programming models and languages for SoC-implemented architectures
Session V: Time and Clocks
Specifying and proving properties of timed I/O automata in the TIOA toolkit
Reliable design with multiple clock domains
The SystemJ approach to system-level design
Keynote Talk III
Integrating design and verification - from simple idea to practical system
Session VI: Scheduling and Analysis
Efficient code generation from synchronous programs
Latency-insensitive design and central repetitive scheduling
A scenario-aware data flow model for combined long-run average and worst-case performance analysis
Poster Presentations: Abstracts
Equivalence checking: a rule-based approach
Formal methods for checking realizability of coalitions in 3-party systems
A semantic-driven synthesis flow for platform-based design
Assertion checking of control dominated systems with nonlinear solvers
Compositional interaction specifications for SystemC
R-SHIM: deterministic concurrency with recursion and shared variables
Author Index

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Session II: Rule-based HW Design

Content Provider ACM Digital Library
Starting Page 37
Ending Page 38
Page Count 2
File Format PDF
ISBN 1424404215
DOI 10.1109/MEMCOD.2006.1695898
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2006-07-27
Access Restriction Subscribed
Content Type Text
Resource Type Article
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