NDLI: Design tradeoffs for tiled CMP on-chip networks ( ICS '06 )

Please wait, while we are loading the content...

A modern high-performance processor pipeline

Experimental evaluation of application-level checkpointing for OpenMP programs

BranchTap: improving performance with very few checkpoints through adaptive speculation control

Scientific applications vs. SPEC-FP: a comparison of program behavior

Efficient remote block-level I/O over an RDMA-capable NIC

A case for high performance computing with virtual machines

Online power-performance adaptation of multithreaded programs using hardware event-based prediction

Design tradeoffs for tiled CMP on-chip networks

Coupling prefix caching and collective downloads for remote dataset access

Accelerator design for protein sequence HMM search

Sensitivity analysis of knapsack-based task scheduling on the grid

User-guided symbiotic space-sharing of real workloads

Cooperative checkpointing: a robust approach to large-scale systems reliability

Selective predicate prediction for out-of-order processors

The exigency of benchmark and compiler drift: designing tomorrow's processors with yesterday's tools

A scalable communication layer for multi-dimensional hyper crossbar network using multiple gigabit ethernet

Implementing virtual memory in a vector processor with software restart markers

A scalable low power issue queue for large instruction window processors

STAR-MPI: self tuned adaptive routines for MPI collective operations

Heterogeneous way-size cache

A distributed system based on web services for computational science simulations

Probabilistic accuracy bounds for fault-tolerant computations that discard tasks

MPIPP: an automatic profile-guided parallel process placement toolset for SMP clusters and multiclusters

On the performance potential of different types of speculative thread-level parallelism: The DL version of this paper includes corrections that were not made available in the printed proceedings

Wide and efficient trace prediction using the local trace predictor

Accurate memory data flow modeling in statistical simulation

Large files, small writes, and pNFS

Multigrid and Gauss-Seidel smoothers revisited: parallelization on chip multiprocessors

Design space exploration for multicore architectures: a power/performance/thermal view

Scaling MPI to short-memory MPPs such as BG/L

Profitable loop fusion and tiling using model-driven empirical search

Accelerating sparse matrix computations via data compression

Violated dependence analysis

Lightweight lock-free synchronization methods for multithreading

Quantum mechanical approaches to information processing

Scalable, fault tolerant membership for MPI tasks on HPC systems

TMA: a trap-based memory architecture

Scalable algorithms for global snapshots in distributed systems

Feedback-directed memory disambiguation through store distance analysis

Design tradeoffs for tiled CMP on-chip networks ( ICS '06 )

Content Provider	ACM Digital Library
Author	Balfour, James Dally, William J.
Abstract	We develop detailed area and energy models for on-chip interconnection networks and describe tradeoffs in the design of efficient networks for tiled chip multiprocessors. Using these detailed models we investigate how aspects of the network architecture including topology, channel width, routing strategy, and buffer size affect performance and impact area and energy efficiency. We simulate the performance of a variety of on-chip networks designed for tiled chip multiprocessors implemented in an advanced VLSI process and compare area and energy efficiencies estimated from our models. We demonstrate that the introduction of a second parallel network can increase performance while improving efficiency, and evaluate different strategies for distributing traffic over the subnetworks. Drawing on insights from our analysis, we present a concentrated mesh topology with replicated subnetworks and express channels which provides a 24% improvement in area efficiency and a 48% improvement in energy efficiency over other networks evaluated in this study.
Starting Page	187
Ending Page	198
Page Count	12
File Format	PDF
ISBN	1595932828
DOI	10.1145/1183401.1183430
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-06-28
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Design tradeoffs for tiled CMP on-chip networks

Author retrospective for design tradeoffs for tiled CMP on-chip networks

ABSTRACT Design Tradeoffs for Tiled CMP On-Chip Networks

Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip

Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip

NoC-aware cache design for multithreaded execution on tiled chip multiprocessors

DiCo-CMP: Efficient cache coherency in tiled CMP architectures

An Innovative Power-Efficient Architecture for Input Buffer of Network on Chip

A survey on cache coherence for tiled many-core processor

Design tradeoffs for tiled CMP on-chip networks ( ICS '06 )

Similar Documents

Design tradeoffs for tiled CMP on-chip networks

Author retrospective for design tradeoffs for tiled CMP on-chip networks

ABSTRACT Design Tradeoffs for Tiled CMP On-Chip Networks

Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip

Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip

NoC-aware cache design for multithreaded execution on tiled chip multiprocessors

DiCo-CMP: Efficient cache coherency in tiled CMP architectures

An Innovative Power-Efficient Architecture for Input Buffer of Network on Chip

A survey on cache coherence for tiled many-core processor

Design tradeoffs for tiled CMP on-chip networks ( ICS '06 )