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  1. Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE '03)
  2. Author Index
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Message from the Chairs
Committee Members and Organizers
Executable Computational Logics: Combining Formal Methods and Programming Language Based System Design
MoDe: A Method for System-Level Architecture Evaluation
From Use Cases to System Implementation: Statechart Based Co-design
Petri Net Based Interface Analysis for Fast IP-Core Integration
Goal-Oriented Requirements Analysis for Process Control Systems Design
Analyzing Concurrency in Computational Networks
Translating Fusion/UML to Object-Z
Finding Good Counter-Examples to Aid Design Verification
High Level Verification of Control Intensive Systems Using Predicate Abstraction
Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Impress Data-Memory Exceptions
Combining ACL2 and a v-calculus Model-Checker to Verify System-Level Designs
Engineering Changes in Field Modifiable Architectures
Hierarchical and Incremental Verification for System Level Design: Challenges and Accomplishments
How to Compute the Refinement Relation for Parameterized Systems
Using SSDE for USB2.0 conformance co-verification
From Algorithm and Architecture Specifications to Automatic Generation of Distributed Real-Time Executives: a Seamless Flow of Graphs Transformations
Methods for exploiting SAT solvers in unbounded model checking
On the Use of a High-Level Fault Model to Check Properties Incompleteness
Exact Runtime Analysis Using Automata-Based Symbolic Simulation
Real-time Property Preservation in Approximations of Timed Systems
Reliability Evaluation for Dependable Embedded System Specifications: An Approach Based on DSPN
Modular Hierarchies of Models for Embedded Systems
Verification of Transaction-Level SystemC models using RTL Testbenches
LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnect
A Generalised Approach to Supervisor Synthesis
Optimizations for Faster Execution of Esterel Programs
Bridging CSP and C++ with Selective Formalism and Executable Specifications
Bluespec: A language for hardware design, simulation, synthesis and verification Invited Talk
A Verification Methodology for Infinite-State Message Passing Systems
Verification of Control Properties in the Polyhedral Model
PANEL: Should the space of implementation possibilities be determined by the abilities of high-level synthesis and validation?
Robust System Design with Uncertain Information
Author Index

Author Index ( MEMOCODE '03 )

Content Provider ACM Digital Library
ISBN 0769519237
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2003-06-24
Access Restriction Subscribed
Content Type Text
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