NDLI: Network-on-chip service guarantees on the kalray MPPA-256 bostan processor

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Content Provider	ACM Digital Library
Author	de Dinechin, Benoît Dupont Graillat, Amaury
Abstract	The Kalray MPPA-256 Bostan manycore processor implements a clustered architecture, where clusters of cores share a local memory, and a DMA-capable network-on-chip (NoC) connects the clusters. The NoC implements wormhole switching without virtual channels, with source routing, and can be configured for maximum flow rate and burstiness at ingress. We describe and illustrate the techniques used to configure the MPPA NoC for guaranteed services. Our approach is based on three steps: global selection of routes between end-points and computation of flow rates, by solving the max-min fairness with unsplittable path problem; configuration of the flow burstiness parameters at ingress, by solving an acyclic set of linear inequalities; and end-to-end latency upper bound computation, based on the principles of separated flow analysis (SFA). In this paper, we develop the two last steps, taking advantage of the effects of NoC link shaping on the leaky-bucket arrival curves of flows.
Starting Page	35
Ending Page	40
Page Count	6
File Format	PDF
ISBN	9781450352260
DOI	10.1145/3073763.3073770
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2017-01-25
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Deterministic network calculus Link traffic shaping Network-on-chip Separated flow analysis
Content Type	Text
Resource Type	Article

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Network-on-chip service guarantees on the kalray MPPA-256 bostan processor