NDLI: Path Prediction For High Issue-Rate Processors

Please wait, while we are loading the content...

Locality Analysis For Parallel C Programs

Heap Analysis And Optimizations For Threaded Programs

Interprocedural Distribution Assignment Placement: More Than Just Enhancing Intraprocedural Placing Techniques

The Effect of Limited Network Bandwidth and its Utilization by Latency Hiding Techniques in Large-scale Shared Memory Systems

Efficient Personalized Communication on Wormhole Networks

Empirical Evaluation Of Deterministic And Adaptive Routing With Constant-Area Routers

A Register Pressure Sensitive Instruction Scheduler for Dynamic Issue Processors

A Parallel Algorithm For Compile-Time Scheduling Of Parallel Programs On Multiprocessors

Path Profile Guided Partial Dead Code Elimination Using Predication

The PROMIS Compiler Prototype

Improving the Memory Bandwidth of Highly-Integrated, Wide-Issue, Microprocessor-Based Systems

Parallel Execution of Radix Sort Program using Fine-grain Communication

Interprocedural Array Remapping

Design of heterogenous multi-processor embedded systems: applying functional pipelining

VLIW Across Multiple Superscalar Processors on a Single Chip

Path Prediction For High Issue-Rate Processors

Buffer-Safe Communication Optimization based on Data Flow Analysis and Performance Prediction

MDL: A Language And Compiler For Dynamic Program Instrumentation

Optimally Synchronizing DOACROSS Loops on Shared Memory Multiprocessors

Two Techniques for Static Array Partitioning on Message-Passing Parallel Machines

Compiler Algorithms For Optimizing Locality And Parallelism On Shared And Distributed Memory Machines

Effective Usage of Vector Registers in Advanced Vector Architectures

Static Locality Analysis for Cache Management

Overcoming Limitations Of Prefetching In Multiprocessors By Compiler-Initiated Coherence Action

Towards a Time and Space Efficient Functional Implementation of a Monte Carlo Photon Transport Code

Direct Generation of Data-Driven Program for Stream-Oriented Processing

Determining the Idle Time of a Tiling: New Results

Index Of Authors

Path Prediction For High Issue-Rate Processors

Content Provider	ACM Digital Library
Author	Sathaye, S. W. Coate, T. M. Menezes, K. N.
Abstract	Rapid developments in the exploitation of instruction-level parallelism are prompting deeper-pipelined, wider machines with high issue rates. Speculative execution has been used to provide the required issue bandwidth. Current methods predict a single branch at a time. Performance improvement is possible by predicting multiple branches in a single cycle. The paper presents a technique to predict paths in a single access. The correlation of a path with the branches executed before it, is exploited to provide high prediction accuracy. A novel path prediction automaton is presented The automaton is easily scalable to predict long paths through arbitrary subgraphs. It also predicts a path through a subgraph in a single access. The automaton requires only n+1 bits for predicting the 2/sup n/ paths in a subgraph of depth n. The performance of the proposed path predictor is measured. The full path accuracy (accuracy in predicting all the branches in a path) is higher than or equal to other predictors found in the literature. This performance is achieved at a low hardware cost. The scalability single access prediction and low hardware cost of the path prediction technique presented in the paper make it suitable for machines requiring high issue bandwidth.
ISBN	0818680903
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1997-11-11
Access Restriction	Subscribed
Subject Keyword	Path prediction automaton Scalability single access prediction Multiple branches Cycle Pipeline processing Instruction-level parallelism Low hardware cost Speculative execution Issue bandwidth Path prediction Arbitrary subgraphs Performance improvement High issue-rate processors
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in