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  1. Proceedings of the 7th International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computing Systems (PMBS '16)
  2. Static cost estimation for data layout selection on GPUs
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HPC benchmarking: problem size matters
An evaluation of network architectures for next generation supercomputers
A performance model for allocating the parallelism in a multigrid-in-time solver
Data-driven performance modeling of linear solvers for sparse matrices
Evaluating and optimizing the NERSC workload on Knights Landing
Performance analysis and optimization of Clang's OpenMP 4.5 GPU support
Effective use of large high-bandwidth memory caches in HPC stencil computation via temporal wave-front tiling
Static cost estimation for data layout selection on GPUs
Visual data-analytics of large-scale parallel discrete-event simulations
Enabling work migration in CoMD to study dynamic load imbalance solutions
Reproducible stencil compiler benchmarks using PROVA!

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Static cost estimation for data layout selection on GPUs

Content Provider ACM Digital Library
Author Peng, Yuhan Sarkar, Vivek Grossman, Max
Abstract Performance modeling provides mathematical models and quantitative analysis for designing and optimizing computer systems. In high performance architectures, high-latency memory accesses often dominate execution time in many classes of applications. Thus, performance modeling for memory accesses of high performance architectures has been an important research topic. In high performance computation, data layout can significantly affect the efficiency of memory access operations. In recent years, the problem of data layout selection has been well studied on various parallel CPU and some GPU architectures. GPUs have memory hierarchies different from multi-core CPUs. While data layout selection on GPUs has been inspected by several existing projects, there is still a lack of a mathematical cost model for data layout selection on GPUs. This motivates us to investigate static cost analysis methods that could better guide future data layout selection work, and perhaps even designing new SIMT architectures. In this paper, we propose a comprehensive cost analysis for data layout selection for GPUs. We build our cost function based on the knowledge of the GPU memory hierarchy, and develop an algorithm which allows researchers to perform compile time cost estimation for a given data layout. Furthermore, we introduce a new vector based representation to represent the estimated cost, which can better estimate the cost of applications with dynamic length loops. We apply our cost analysis to selected benchmarks from past publications on data layout selection. Our experimental results show that our cost analysis can accurately predict the relative costs of different data layouts. Using the cost model presented in this paper, we are developing an automatic data layout selection tool in our ongoing work.
Starting Page 76
Ending Page 86
Page Count 11
ISBN 9781509052189
DOI 10.1109/PMBS.2016.13
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2016-11-13
Access Restriction Subscribed
Subject Keyword Cost estimation Cost vector Gpu Data layout selection
Content Type Text
Resource Type Article
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