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| Content Provider | ACM Digital Library |
|---|---|
| Author | Daneshtalab, Masoud Gaur, Manoj Singh Kumar, Manoj Gupta, Niyati Ebrahimi, Masoumeh Laxmi, Vijay Sharma, Ashish |
| Abstract | With the emergence of large multi-core architectures, a volume of research has been focused on distributing traffic evenly over the whole network. However, increase in traffic density may lead to congestion and subsequently degrade the performance by increased latency in the network. In this paper, we propose two novel route selection strategies for on-chip networks which are based on the Q-learning framework. The proposed strategies use variable learning rate to dynamically capture the current congestion status of the network using an additional parameter and improves the learning process to select a less congested output channel. Both the proposed selection strategies are found to adapt significantly faster to the changes in traffic load and traffic patterns by avoiding congested areas. The results demonstrate that proposed strategies achieve significant performance improvement over conventional Q-routing and its variants with slight area-overhead. |
| Starting Page | 33 |
| Ending Page | 40 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781450334082 |
| DOI | 10.1145/2768177.2768180 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2015-06-13 |
| Publisher Place | New York |
| Access Restriction | Subscribed |
| Subject Keyword | Q-learning Q-routing Congestion On-chip networks |
| Content Type | Text |
| Resource Type | Article |
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