NDLI: TurboSMARTS: accurate microarchitecture simulation sampling in minutes

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TurboSMARTS: accurate microarchitecture simulation sampling in minutes

Content Provider	ACM Digital Library
Author	Wenisch, Thomas F. Hoe, James C. Wunderlich, Roland E. Falsafi, Babak
Abstract	Recent research proposes accelerating processor microarchitecture simulation through statistical sampling. Prior simulation sampling approaches construct accurate model state for each measurement by continuously warming large microarchitectural structures (e.g., caches and the branch predictor) while emulating the billions of instructions between measurements. This approach, called functional warming, occupies hours of runtime while the detailed simulation that is measured requires mere minutes.To eliminate the functional warming bottleneck, we propose TurboSMARTS, a simulation framework that stores functionally-warmed state in a library of small, reusable checkpoints. TurboSMARTS enables the creation of the thousands of checkpoints necessary for accurate sampling by storing only the subset of warmed state accessed during simulation of each brief execution window. TurboSMARTS matches the accuracy of prior simulation sampling techniques (i.e., ±3% error with 99.7% confidence), while estimating the performance of an 8-way out-of-order super-scalar processor running SPEC CPU2000 in 91 seconds per benchmark, on average, using a 12 GB checkpoint library.
Starting Page	408
Ending Page	409
Page Count	2
File Format	PDF
ISBN	1595930221
DOI	10.1145/1064212.1064278
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2005-06-06
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Checkpointed microarchitecture simulation Simulation sampling
Content Type	Text
Resource Type	Article

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