NDLI: Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs

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Constructing exact octagonal steiner minimal trees

Iterative decoding in analog CMOS

Information storage capacity of crossbar switching networks

Power-aware pipelined multiplier design based on 2-dimensional pipeline gating

A novel architecture for power maskable arithmetic units

Shielding effect of on-chip interconnect inductance

Design topology aware physical metrics for placement analysis

Simultaneous peak and average power minimization during datapath scheduling for DSP processors

Orthogonal code generator for 3G wireless transceivers

On automatic generation of RTL validation test benches using circuit testing techniques

Bounding the efforts on congestion optimization for physical synthesis

Design issues in low-voltage high-speed current-mode logic buffers

Exploiting multiple functionality for nano-scale reconfigurable systems

Low power VLSI sequential circuit architecture using critical race control

3D direct vertical interconnect microprocessors test vehicle

A pipelined clock-delayed domino carry-lookahead adder

A novel ultra-fast heuristic for VLSI CAD steiner trees

Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs

54x54-bit radix-4 multiplier based on modified booth algorithm

A highly regular multi-phase reseeding technique for scan-based BIST

A comprehensive high-level synthesis system for control-flow intensive behaviors

Optimum wire sizing of RLC interconnect with repeaters

CMOS flash analog-to-digital converter for high speed and low voltage applications

A hybrid adiabatic content addressable memory for ultra low-power applications

Zero overhead watermarking technique for FPGA designs

A globally asynchronous locally dynamic system for ASICs and SoCs

Combining wire swapping and spacing for low-power deep-submicron buses

Branch prediction techniques for low-power VLIW processors

Power-time flexible architecture for $GF(2^{k})$ elliptic curve cryptosystem computation

Coefficient-based parametric faults detection in analog circuits

Reduced dynamic swing domino logic

Modeling QCA for area minimization in logic synthesis

TEM-cell and surface scan to identify the electromagnetic emission of integrated circuits

Matrix datapath architecture for an iterative 4x4 MIMO noise whitening algorithm

40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications

Clustering based acyclic multi-way partitioning

A novel 32-bit scalable multiplier architecture

Mixing ATPG and property checking for testing HW/SW interfaces

A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology

MuTaTe: an efficient design for testability technique for multiplexor based circuits

System level design of real time face recognition architecture based on composite PCA

Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing

High throughput overlapped message passing for low density parity check codes

Interconnected rings and oscillators as gigahertz clock distribution nets

Cooling of integrated circuits using droplet-based microfluidics

Design and modeling of a 16-bit 1.5MSPS successive approximation ADC with non-binary capacitor array

Congestion reduction in traditional and new routing architectures

Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers

Language emptiness checking using MDGs

Using dynamic domino circuits in self-timed systems

A system-level methodology for fast multi-objective design space exploration

Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs

A practical CAD technique for reducing power/ground noise in DSM circuits

Comparison of noise tolerant precharge (NTP) to conventional feedback keepers for dynamic logic

RF CMOS circuit optimizing procedure and synthesis tool

Variable gain amplifier with offset cancellation

Wirelength reduction by using diagonal wire

Repeater and current-sensing hybrid circuits for on-chip interconnects

A fast simulation approach for inductive effects of VLSI interconnects

A slew rate enhancement technique for operational amplifiers based on a tunable active Gm-based capacitance multiplication circuit

Buffer sizing for minimum energy-delay product by using an approximating polynomial

A dual band CMOS VCO with a balanced duty cycle buffer

FORCE: a fast and easy-to-implement variable-ordering heuristic

New approach to CMOS current reference with very low temperature coefficient

Routing methodology for minimizing 1nterconnect energy dissipation

Noise tolerant low voltage XOR-XNOR for fast arithmetic

Circuit design of a wide tuning range CMOS VCO with automatic amplitude control

A decoupling technique for CMOS strong-coupled structures

A custom FPGA for the simulation of gene regulatory networks

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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