NDLI: Two techniques for reconciling algorithm parallelism with memory constraints

Content Provider	ACM Digital Library
Author	Vishkin, Uzi
Abstract	The utility of algorithm parallelism for coping with increased processor to memory latencies using "latency hiding" is part of the folklore of parallel computing. Latency hiding techniques increase the traffic to memory and therefore may "hit another wall": limited bandwidth to memory. The current paper attempts to stimulate research in the following general direction: show that algorithm parallelism need not conflict with limited bandwidth.A general technique for using parallel algorithms to enhance serial implementation in the face of processor-memory latency problems is revisited. Two techniques for alleviating memory bandwidth constraints are presented. Both techniques can be incorporated in a compiler.There is often considerable parallelism in many of the algorithms which are known as useful serial algorithms. Interestingly enough, all the examples provided for the use of the two techniques come from such serial algorithms.
Starting Page	95
Ending Page	98
Page Count	4
File Format	PDF
ISBN	1581135297
DOI	10.1145/564870.564884
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2002-08-10
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Prefetching Memory systems constraints Parallel algorithms
Content Type	Text
Resource Type	Article

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Two techniques for reconciling algorithm parallelism with memory constraints