NDLI: Physical limitations on the bit-rate of on-chip interconnects

Please wait, while we are loading the content...

On-chip power distribution grids with multiple supply voltages for high performance integrated circuits

Physical limitations on the bit-rate of on-chip interconnects

Instruction scheduling using MAX-MIN ant system optimization

Characterizing the VCO jitter due to the digital simultaneous switching noise

Untestable fault identification through enhanced necessary value assignments

Tile-based design of a serial memory in QCA

DIP: a double-interval-based dynamic voltage scaling scheme for dynamic priority-based task scheduling systems

An effective and efficient ATPG-based combinational equivalence checker

Energy management in software-controlled multi-level memory hierarchies

A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach

A hardware/software codesign approach for programmable IO devices

1-V 7-mW dual-band fast-locked frequency synthesizer

Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing

A novel buffer circuit for energy efficient signaling in dual-VDD systems

Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits

Variability modeling and variability-aware design in deep submicron integrated circuits

Low power test generation for path delay faults using stability functions

Interconnect delay minimization through interlayer via placement in 3-D ICs

A unified processor architecture for RISC & VLIW DSP

Exact minimum-width transistor placement without dual constraint for CMOS cells

Test set enhancement for quality transition faults using function-based methods

Multi-GHz SiGe design methodologies for reconfigurable computing

Energy optimization in memory address bus structure for application-specific systems

Forward image computation with backtracing ATPG and incremental state-set construction

Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors

A complete methodology for an accurate static noise analysis

Analysis and design of soft-error hardened latches

Increasing the energy efficiency of pipelined circuits via slack redistribution

LiPaR: A light-weight parallel router for FPGA-based networks-on-chip

Energy recovery clocked dynamic logic

A congestion-driven placement framework with local congestion prediction

Research and development for seamless mobility

Thermal aware cell-based full-chip electromigration reliability analysis

Zero clustering: an approach to extend zero compression to instruction caches

High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping

Two dimensional reordering of functional test data for compression by ATE

Low-power circuits using dynamic threshold devices

Fine-grain leakage optimization in SRAM based FPGAs

Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning

Load elimination for low-power embedded processors

A new approach to the use of satisfiability in false path detection

Clock skew bounds estimation under power supply and process variations

Adaptive digital techniques to suppress quantization noise of ΣΔ analog to digital converters

3D module placement for congestion and power noise reduction

Adaptive gate biasing: a new solution for body-driven current mirrors

Reticle floorplanning of flexible chips for multi-project wafers

Accounting for the skin effect during repeater insertion

A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology

An improved direct boundary element method for substrate coupling resistance extraction

Diagnosing multiple transition faults in the absence of timing information

QCA channel routing with wire crossing minimization

A sensitivity analysis of low-power repeater insertion

Utilizing don't care states in SAT-based bounded sequential problems

An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs

Optimization objectives and models of variation for statistical gate sizing

Tool integration using the web-services approach

A high speed and leakage-tolerant domino logic for high fan-in gates

A study of tighter lower bounds in LP relaxation based placement

Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution

PIM lite: a multithreaded processor-in-memory prototype

Generating decision regions in analog measurement spaces

An EFSM-based approach for functional ATPG

A new algorithm for layout of dark field alternating phase shifting masks

A VLSI array processing oriented fast fourier transform algorithm and hardware implementation

An empirical study of crosstalk in VDSM technologies

VLSI CAD tool protection by birthmarking design solutions

Integer linear programming based energy optimization for banked DRAMs

A continuous time markov decision process based on-chip buffer allocation methodology

Slack borrowing in flip-flop based sequential circuits

The $G^{4}-FET:$ a universal and programmable logic gate

On equivalence checking and logic synthesis of circuits with a common specification

Using data compression in an MPSoC architecture for improving performance

Quantum-dot cellular automata SPICE macro model

Dual-transition glitch filtering in probabilistic waveform power estimation

Causal probabilistic input dependency learning for switching model in VLSI circuits

SOFTENIT: a methodology for boosting the software content of system-on-chip designs

Area-efficient two-dimensional architectures for finite field inversion and division

Low-overhead state-retaining elements for low-leakage MTCMOS design

2.5GHz PLL with current matching charge-pump for 10Gbps transmitter design

Enhancing error resilience for reliable compression of VLSI test data

The oct-touched tile: a new architecture for shape-based routing

Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs

System level design language extensions for timed/untimed digital-analog combined system design

Total leakage optimization strategies for multi-level caches

Noise-tolerant high fan-in dynamic CMOS circuit design

Design of a cell library for asynchronous microengines

Noise aware behavioral modeling of the Ε-Δ fractional-N frequency synthesizer

Moment-driven coupling-aware routing methodology

Improved multilevel routing with redundant via placement for yield and reliability

New algorithms for carry propagation

An FPGA design of AES encryption circuit with 128-bit keys

Exploiting PSL standard assertions in a theorem-proving-based verification environment

High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion

Increasing design space of the instruction queue with tag coding

Fixed-outline floorplanning based on common subsequence

Characterization of monotonic static CMOS gates in a 65nm technology

Interconnect capacitance extraction for system LCD circuits

An analysis of the robustness of CMOS delay elements

Two-prime RSA immune cryptosystem and its FPGA implementation

A first look at the interplay of code reordering and configurable caches

A simple wide-band compact model and parameter extraction using particle swarm optimization of on-chip spiral inductors for silicon RFICs

FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks

Digital cell macro-model with regular substrate template and EKV based MOSFET model

VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input

Physical limitations on the bit-rate of on-chip interconnects

Content Provider	ACM Digital Library
Author	Ghoneima, Maged Ismail, Yehia Mahmoud, Noha
Abstract	It is shown in this paper that contrary to the common conception, widening an on-chip interconnect wire will not cause the wire to behave as a lossless line. It is shown that the energy losses actually increase when widening a wire. The damping factor of the line, which determines the maximum bit rate that can be transmitted on a wire, also does not go to zero for wide wires as in lossless lines. This fact results in a serious physical limitation on the maximum bit rate that can be transmitted on a wire. It is shown that by increasing the cross-sectional width of an interconnect wire, the damping factor will saturate to a certain limit. An expression for this minimum damping factor for very wide wires is derived from fundamental physical constants and used to introduce an expression for the maximum bit rate that can be reached by widening an interconnect wire for a certain technology. It is shown that for current technology numbers, the maximum bit rate on a wire can be quite limiting for longer wires and that scaling trends will even decrease more this maximum bit rate, posing a serious limitation.
Starting Page	13
Ending Page	19
Page Count	7
File Format	PDF
ISBN	1595930574
DOI	10.1145/1057661.1057668
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2005-04-17
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Damping factor Interconnects Bit-rate Delay
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in