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| Content Provider | ACM Digital Library |
|---|---|
| Author | Khatri, Sunil P. Abusultan, Monther Fairouz, Abbas |
| Abstract | Modern microprocessors contain several Special Function Units (SFUs) such as specialized arithmetic units, cryptographic processors, etc. In recent times, applications such as cloud computing, web-based search engines, and network applications are widely used, and place new demands on the microprocessor. Hashing is a key algorithm that is extensively used in such applications. Hashing is typically performed in software. Thus, implementing a hardware-based hash unit on a modern microprocessor would potentially increase performance significantly. In this paper, we present the circuit design for a hardware hash unit (HU) for modern microprocessors, using a 45nm technology. Our proposed hardware hash unit is based on the use of a CAM to implement each bin of the hash function. We simulate the HU circuit and compare it with a traditional CAM design. We demonstrate an average power reduction of 5.48x using the HU over the traditional CAM. Also, we show that the HU can operate at a maximum frequency of 1.39 GHz (after accounting for process, voltage and temperature (PVT) variations and accounting for wiring parasitics). Furthermore, we present the delay, power and area trade-offs of the HU design with varying hash table sizes. |
| Starting Page | 101 |
| Ending Page | 106 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781450349727 |
| DOI | 10.1145/3060403.3060451 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2017-05-10 |
| Publisher Place | New York |
| Access Restriction | Subscribed |
| Subject Keyword | Hardware hash unit Special function unit Hash function Content-addressable memory Hash table Modern microprocessors |
| Content Type | Text |
| Resource Type | Article |
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