NDLI: Wall street evaluates EDA

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Wall street evaluates EDA

IP delivery for FPGAs using Applets and JHDL

A universal technique for fast and flexible instruction-set architecture simulation

A factorization-based framework for passivity-preserving model reduction of RLC systems

Uncertainty-aware circuit optimization

Tools or users: which is the bigger bottleneck?

Life is CMOS: why chase the life after?

Efficient state representation for symbolic simulation

RTL c-based methodology for designing and verifying a multi-threaded processor

Automated timing model generation

The wearable motherboard: a framework for personalized mobile information processing (PMIP)

Analog intellectual property: now? Or never?

Task scheduling and voltage selection for energy minimization

River PLAs: a regular circuit structure

Automatic data migration for reducing energy consumption in multi-bank memory systems

Multifunctional photonic integration for the agile optical internet

Nanometer design: what hurts next...?

Low-cost sequential ATPG with clock-control DFT

Design of a high-throughput low-power IS95 Viterbi decoder

Transformation based communication and clock domain refinement for system design

Automated equivalence checking of switch level circuits

Whither (or wither?) ASIC handoff?

Software synthesis from synchronous specifications using logic simulation techniques

Exploiting operation level parallelism through dynamically reconfigurable datapaths

Embedded software-based self-testing for SoC design

Going mobile: the next horizon for multi-million gate designs in the semi-conductor industry

HiPRIME:: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery

Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems

An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits

Petri net modeling of gate and interconnect delays for power estimation

Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant?

Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits

System-level performance optimization of the data queueing memory management in high-speed network processors

Behavioral modeling of (coupled) harmonic oscillators

A general probabilistic framework for worst case timing analysis

Formal verification methods: getting around the brick wall

S-Tree: a technique for buffered routing tree synthesis

Automatic generation of embedded memory wrapper for multiprocessor SoC

Schedulability of event-driven code blocks in real-time embedded systems

Unlocking the design secrets of a 2.29 Gb/s Rijndael processor

What's the next EDA driver?

Estimation of the likelihood of capacitive coupling noise

Reduction of SOC test data volume, scan power and testing time using alternating run-length codes

Communication architecture based power management for battery efficient system design

Embedding infrastructure IP for SOC yield improvement

A proof engine approach to solving combinational design automation problems

A solenoidal basis method for efficient inductance extraction

System design methodologies for a wireless security processing platform

Deriving a simulation input generator and a coverage metric from a formal specification

Energy-efficient communication protocols

TCG-S: orthogonal coupling of P*-admissible representations for general floorplans

Coping with buffer delay change due to power and ground noise

A framework for evaluating design tradeoffs in packet processing architectures

Coordinated transformations for high-level synthesis of high performance microprocessor blocks

Watermarking integer linear programming solutions

A fast on-chip profiler memory

Model order reduction for strictly passive and causal distributed systems

Congestion-driven codesign of power and signal networks

The next chip challenge: effective methods for viable mixed technology SoCs

Handling special constructs in symbolic simulation

High-Level specification and automatic generation of IP interface monitors

Timing model extraction of hierarchical blocks by graph reduction

Challenges and opportunities in electronic textiles modeling and optimization

Battery-conscious task sequencing for portable devices including voltage/clock scaling

Layout-aware synthesis of arithmetic circuits

Exploiting shared scratch pad memory space in embedded multiprocessor systems

Computer aided design of long-haul optical transmission systems

Effective diagnostics through interval unloads in a BIST environment

A detailed cost model for concurrent use with hardware/software co-design

Model composition for scheduling analysis in platform design

A practical and efficient method for compare-point matching

Complex library mapping for embedded software using symbolic algebra

Dynamic hardware plugins in an FPGA with partial run-time reconfiguration

A novel wavelet transform based transient current analysis for fault detection and localization

High-level current macro-model for power-grid analysis

Design of asynchronous circuits by synchronous CAD tools

Remembrance of circuits past: macromodeling by data mining in large analog design spaces

Power estimation in global interconnects and its reduction using a novel repeater optimization methodology

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors

Time-domain steady-state simulation of frequency-dependent components using multi-interval Chebyshev method

Analysis of power consumption on switch fabrics in network routers

Model checking algorithms for analog verification

False timing path identification using ATPG techniques and delay-based information

An algorithm for integrated pin assignment and buffer planning

A novel synthesis technique for communication controller hardware from declarative data communication protocol specifications

Associative caches in formal software timing analysis

The iCOREtm 520 MHz synthesizable CPU core

Crosstalk noise estimation for noise management

Embedded test control schemes for compression in SOCs

Scheduler-based DRAM energy management

Using embedded FPGAs for SoC yield improvement

Solving difficult SAT instances in the presence of symmetry

On the efficacy of simplified 2D on-chip inductance models

Constraint-driven communication synthesis

Hole analysis for functional coverage data

Reliable and energy-efficient digital signal processing

Floorplanning with alignment and performance constraints

Osculating Thevenin model for predicting delay and slew of capacitively characterized cells

Energy estimation and optimization of embedded VLIW processors based on instruction clustering

Forward-looking objective functions: concept & applications in high level synthesis

Model design using hierarchical web-based libraries

Design of an one-cycle decompression hardware for performance increase in embedded systems

Guaranteed passive balancing transformations for model order reduction

On metrics for comparing routability estimation methods for FPGAs

Few electron devices: towards hybrid CMOS-SET integrated circuits

A hybrid verification approach: getting deep into the design

Achieving maximum performance: a method for the verification of interlocked pipeline control logic

Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparency

An energy saving strategy based on adaptive loop parallelization

Address assignment combined with scheduling in DSP code generation

A fast optical propagation technique for modeling micro-optical systems

On output response compression in the presence of unknown output values

Efficient code synthesis from extended dataflow graphs for multimedia applications

Timed compiled-code simulation of embedded software for performance analysis of SOC design

Self-referential verification of gate-level implementations of arithmetic circuits

Retargetable binary utilities

A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator

Signal integrity fault analysis using reduced-order modeling

Macro-modeling concepts for the chip electrical interface

Implementing asynchronous circuits using a conventional EDA tool-flow

Optimal design of delta-sigma ADCs by design space exploration

Low-swing clock domino logic incorporating dual supply and dual threshold voltages

An optimal voltage synthesis technique for a power-efficient satellite application

A time-domain RF steady-state method for closely spaced tones

Memory optimization in single chip network switch fabrics

Regularization of hierarchical VHDL-AMS models using bipartite graphs

False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

An efficient routing database

An integrated algorithm for memory allocation and assignment in high-level synthesis

Compiler-directed scratch pad memory hierarchy design and management

A flexible accelerator for layer 7 networking applications

Variable frequency crosstalk noise analysis: a methodology to guarantee functionality from dc to $f_{max}$

Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs

An integer linear programming based approach for parallelizing applications in On-chip multiprocessors

Satometer:: how much have we searched?

A physical model for the transient response of capacitively loaded distributed rlc interconnects

Component-based design approach for multicore SoCs

Effective safety property checking using simulation-based sequential ATPG

CMOS: a paradigm for low power wireless?

Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control

Timed pattern generation for noise-on-delay calculation

Energy exploration and reduction of SDRAM memory systems

ILP-based engineering change

Behavioral synthesis via engineering change

Carbon nanotube field-effect transistors and logic circuits

Can BDDs compete with SAT solvers on bounded model checking?

Formal verification of module interfaces against real time specifications

An implication-based method to detect multi-cycle paths in large sequential circuits

Software-based diagnosis for processors

Enhancing test efficiency for delay fault testing using multiple-clocked schemes

Modeling and analysis of regular symmetrically structured power/ground distribution networks

Transformation rules for designing CNOT-based quantum circuits

Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter

DRG-cache: a data retention gated-ground cache for low power

An algorithm for frequency-domain noise analysis in nonlinear systems

Improving the generality of the fictitious magnetic charge approach to computing inductances in the presence of permeable materials

A fast, inexpensive and scalable hardware acceleration technique for functional simulation

High-level synthesis of multiple-precision circuits independent of data-objects length

Towards global routing with RLC crosstalk constraints

SAT with partial clauses and back-leaps

HSpeedEx: a high-speed extractor for substrate noise analysis in complex mixed signal SOC

Traffic analysis for on-chip networks design of multimedia applications

A comparison of three verification techniques: directed testing, pseudo-random testing and property checking

VeriCDF: a new verification methodology for charged device failures

Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients

Fast three-level logic minimization based on autosymmetry

Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver

Combined BEM/FEM substrate resistance modeling

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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