NDLI: TLM automation for multi-core design

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A PUF design for secure FPGA-based embedded systems

Efficient model reduction of interconnects via double gramians approximation

Simultaneous slack budgeting and retiming for synchronous circuits optimization

Room-temperature fuel cells and their integration into portable and embedded systems

Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memory

On-chip power network optimization with decoupling capacitors and controlled-ESRs

Speeding up SoC virtual platform simulation by data-dependency-aware synchronization and scheduling

Design of networks on chips for 3D ICs

Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis

Current source modeling in the presence of body bias

Constrained global scheduling of streaming applications on MPSoCs

Data learning based diagnosis

CrossRouter: a droplet router for cross-referencing digital microfluidic biochips

A performance-constrained template-based layout retargeting algorithm for analog integrated circuits

Technology mapping with crosstalk noise avoidance

Checker-pattern and shared two pixels LOFIC CMOS image sensors

A fast symbolic computation approach to statistical analysis of mesh networks with multiple sources

Scan-based attack against elliptic curve cryptosystems

Optimizing power and performance for reliable on-chip networks

Design and verification methods of Toshiba's wireless LAN baseband SoC

A dual-MST approach for clock network synthesis

Improved weight assignment for logic switching activity during at-speed test pattern generation

Application-specific 3D Network-on-Chip design using simulated allocation

Is 3D integration an opportunity or just a hype?

Configurable multi-product floorplanning

An analytical dynamic scaling of supply voltage and body bias exploiting memory stall time variation

Managing verification error traces with bounded model debugging

Resilient design in scaled CMOS for energy efficiency

A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography

Statistical timing verification for transparently latched circuits through structural graph traversal

Minimizing leakage power in aging-bounded high-level synthesis with design time $multi-V_{th}$ assignment

Computer-aided recoding for multi-core systems

Analyzing electrical effects of RTA-driven local anneal temperature variation

Incremental solution of power grids using random walks

Parametric yield driven resource binding in behavioral synthesis with $multi-V_{th}/V_{dd}$ library

-Possibility of ESL-: a software centric system design for multicore SoC in the upstream phase

Slack redistribution for graceful degradation under voltage overscaling

Rule-based optimization of reversible circuits

Hybrid dynamic energy and thermal management in heterogeneous embedded multiprocessor SoCs

MPSoC programming using the MAPS compiler

Adaptive power management for real-time event streams

Wideband reduced modeling of interconnect circuits by adaptive complex-valued sampling method

A fast SPFD-based rewiring technique

Maximizing the harvested energy for micro-power applications through efficient MPPT and PMU design

A new compilation technique for SIMD code generation across basic block boundaries

An adaptive parallel flow for power distribution network simulation using discrete Fourier transform

SCGPSim: a fast SystemC simulator on GPUs

Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs

Manifold construction and parameterization for nonlinear manifold-based model reduction

Analyzing impact of multiple ABB and AVS domains on throughput of power and thermal-constrained multi-core processors

Post-silicon debugging for multi-core designs

Optimal simultaneous pin assignment and escape routing for dense PCBs

Symmetry-aware TCG-based placement design under complex multi-group constraints for analog circuit layouts

Fault-tolerant resynthesis with dual-output LUTs

A CMOS image sensor with $2.0-e^{-}$ random noise and $110-ke^{-}$ full well capacity using column source follower readout circuits

Minimizing clock latency range in robust clock tree synthesis

Secure and testable scan design using extended de Bruijn graphs

A low latency wormhole router for asynchronous on-chip networks

SOC for car navigation system with a 55.3GOPS image recognition engine

Buffered clock tree sizing for skew minimization under power and thermal budgets

Graph partition based path selection for testing of small delay defects

A3MAP: architecture-aware analytic mapping for networks-on-chip

An industrial perspective of 3D IC integration technology: from the viewpoint of design technology

UFO: unified convex optimization algorithms for fixed-outline floorplanning

Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design

Automatic assertion extraction via sequential data mining of simulation traces

Benefits and barriers for probabilistic design

A robust pixel-based RET optimization algorithm independent of initial conditions

A unified multi-corner multi-mode static timing analysis engine

A global interconnect reduction technique during high level synthesis

TLM automation for multi-core design

Physical design techniques for optimizing RTA-induced variations

Efficient power grid integrity analysis using on-the-fly error check and reduction

Optimizing blocks in an SoC using symbolic code-statement reachability analysis

Design of complex image processing systems in ESL

A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs

Variation tolerant logic mapping for crossbar array nano architectures

Energy efficient joint scheduling and multi-core interconnect design

System-level development of embedded software

An alternative polychronous model and synthesis methodology for model-driven embedded software

VISA: versatile impulse structure approximation for time-domain linear macromodeling

iRetILP: an efficient incremental algorithm for min-period retiming under general delay model

Dynamic power management in environmentally powered systems

LibGALS: a library for GALS systems design and modeling

Technique for controlling power-mode transition noise in distributed sleep transistor network

A flexible hybrid simulation platform targeting multiple configurable processors SoC

A novel si-tunnel FET based SRAM design for ultra low-power 0.3V $V_{DD}$ applications

A fast analog mismatch analysis by an incremental and stochastic trajectory piecewise linear macromodel

Source-level timing annotation for fast and accurate TLM computation model generation

Low-cost design for repair with circuit partitioning

CAFE router: a fast connectivity aware multiple nets routing algorithm for routing grid with obstacles

Regularity-oriented analog placement with diffusion sharing and well island generation

TRECO: dynamic technology remapping for timing engineering change orders

Checkered white-RGB color LOFIC CMOS image sensor

Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization

Correlating system test Fmax with structural test Fmax and process monitoring measurements

Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs

Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating

Functional and partially-functional skewed-load tests

Efficient throughput-guarantees for latency-sensitive networks-on-chip

Homogeneous integration for 3D IC with TSV

Fixed-outline thermal-aware 3D floorplanning

Dynamic power estimation for deep submicron circuits with process variation

Automatic constraint generation for guided random simulation

A probabilistic Boolean logic for energy efficient circuit and system design

A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effects

Statistical time borrowing for pulsed-latch circuit designs

Incremental high-level synthesis

Platform modeling for exploration and synthesis

On confidence in characterization and application of variation models

PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization

High level event driven thermal estimation for thermal aware task allocation and scheduling

PAC duo system power estimation at ESL

On process-aware 1-D standard cell design

Generalised threshold gate synthesis based on AND/OR/NOT representation of Boolean function

Dynamic and adaptive allocation of applications on MPSoC platforms

Trace-based performance analysis framework for heterogeneous multicore systems

An extension of the generalized Hamiltonian method to S-parameter descriptor systems

Micro-scale energy harvesting: a system design perspective

Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banks

A novel FDTD algorithm based on alternating-direction explicit method with PML absorbing boundary condition

A fast heuristic scheduling algorithm for periodic ConcurrenC models

CAD reference flow for 3D via-last integrated circuits

Formal verification of tunnel diode oscillator with temperature variations

Improved on-chip router analytical power and area modeling

On signal tracing in post-silicon validation

Obstacle-aware longest path using rectangular pattern detouring in routing grids

A novel characterization technique for high speed I/O mixed signal circuit components using random jitter injection

Multi-operand adder synthesis on FPGAs using generalized parallel counters

A versatile recognition processor for sensor network applications

Improved clock-gating control scheme for transparent pipeline

Guided gate-level ATPG for sequential circuits using a high-level test generation approach

Workload capacity considering NBTI degradation in multi-core systems

Clock tree embedding for 3D ICs

Emulating and diagnosing IR-drop by using dynamic SDF

Floorplanning and topology generation for application-specific network-on-chip

A hierarchical bin-based legalizer for standard-cell designs with minimal disturbance

Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors

A method for debugging of pipelined processors in formal verification by correspondence checking

Dead via minimization by simultaneous routing and redundant via insertion

Design time body bias selection for parametric yield improvement

A high-level synthesis flow for custom instruction set extensions for application-specific processors

Application of ESL synthesis on GSM edge algorithm for base station

Gate delay estimation in STA under dynamic power supply noise

Mapping and scheduling of parallel C applications with ant colony optimization onto heterogeneous reconfigurable MPSoCs

A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an example

D-A converter based variation analysis for analog layout design

Novel $dual-V_{th}$ independent-gate FinFET circuits

Cool and save: cooling aware dynamic workload scheduling in multi-socket CPU systems

Energy and performance driven circuit design for emerging phase-change memory

A 2-6 GHz fully integrated tunable CMOS power amplifier for multi-standard transmitters

An embedded debugging/performance monitoring engine for a tile-based 3D graphics SoC development

Cascaded time difference amplifier using differential logic delay cell

Built-in self at-speed delay binning and calibration mechanism in wireless test platform

Dynamic voltage domain assignment technique for low power performance manageable cell based design

Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits

A 60GHz direct-conversion transmitter in 65nm CMOS technology

An electrically adjustable 3-terminal regulator with post-fabrication level-trimming function

Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing

Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating

A WiMAX turbo decoder with tailbiting BIP architecture

Temporal circuit partitioning for a 90nm CMOS multi-context FPGA and its delay measurement

Design and chip implementation of an instruction scheduling free ubiquitous processor

MuCCRA-3: a low power dynamically reconfigurable processor array

Rapid prototyping on a structured ASIC fabric

A high performance low complexity joint transceiver for closed-loop MIMO applications

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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