NDLI: Determination of UART Receiver Baud Rate Tolerance

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Determination of UART Receiver Baud Rate Tolerance

Content Provider	ACM Digital Library
Author	Singh, Amrit Mala, Juhee Gupta, Khushboo
Abstract	UART is one of the most widely used serial communication protocol in semiconductor domain, and proves to be an integral part of a system irrespective of the industry being used in, extending from Automotive to Industrial to Consumer. A complete system can consist of heterogeneous devices communicating with each other through UART interface, where each such device is capable of generating a different baud rate depending upon its source clock, also known as Baud Clock (which could be derived from PLLs or Oscillator). The Basic Principle of UART Protocol defines that the Transmitter and Receiver should be configured at the same baud rate to communicate correctly. There are some clock dividers implemented within and/or external to the module in order to achieve the same. But it is fairly likely that the baud clocks of two communicating devices are different inspite of having configured the clock dividers properly, leading to a mismatch in the baud rate achieved for both the devices thereby causing Bit Corruption at the receiver. Such a baud rate mismatch can be attributed to the following two factors: 1. Baud Clock inaccuracies 2. Limited clock divider range In this paper, we intend to describe the method of determining the acceptable difference between the transmitter and receiver baud rates, in order to do Error Free Communication through UART.
Starting Page	265
Ending Page	270
Page Count	6
File Format	PDF
ISBN	9781450335522
DOI	10.1145/2818567.2818655
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-09-25
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Configurable sample point (csp) Uart Bit corruption Receiver Bit-rate tolerance Over sampling (osp) Baud rate
Content Type	Text
Resource Type	Article

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