NDLI: Improvements on the detection of false paths by using unateness and satisfiability

Content Provider	ACM Digital Library
Author	Martinello, Osvaldo Marques, Felipe S. Ribas, Renato P. Reis, André I.
Abstract	This paper presents improvements on a previous methodology for false path detection using satisfiability. As the previous methodology, which is referred as node-sat, it is based on circuit node properties that are related to non-testable stuck-at faults as well as to false path detection. When compared to traditional satisfiability methods that generate sets of clauses associated to paths, the node-sat can be more efficient. This efficiency derives from the fact that most digital circuits have a number of nodes that is smaller than the number of paths, and therefore, a smaller number of satisfiability instances needs to be solved. This number can be reduced even more by considering the circuit topology. Experiments comparing the previous node-sat methodology and the new techniques presented on this paper reveal that the execution time is reduced by 60% on average.
Starting Page	192
Ending Page	197
Page Count	6
File Format	PDF
ISBN	9781450301527
DOI	10.1145/1854153.1854201
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-09-06
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	False paths Unateness Satisfiability
Content Type	Text
Resource Type	Article

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Improvements on the detection of false paths by using unateness and satisfiability