NDLI: DART: a programmable architecture for NoC simulation on FPGAs

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Prevention flow-control for low latency torus Networks-on-Chip

BLOCON: a bufferless photonic Clos Network-on-Chip architecture

Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration

FIST: A Fast, Lightweight, FPGA-Friendly Packet Latency Estimator for NoC Modeling in Full-System Simulations

Complex network inspired fault-tolerant NoC architectures with wireless links

Dynamic decentralized mapping of tree-structured applications on NoC architectures

Curbing energy cravings in networks: a cross-sectional view across the micro-macro boundary

The XMOS XK-XMP-64 development board

Analysis of application-aware on-chip routing under traffic uncertainty

A vertical bubble flow network using inductive-coupling for 3-D CMPs

Two-hop free-space based optical interconnects for chip multiprocessors

A distributed and topology-agnostic approach for on-line NoC testing

DART: a programmable architecture for NoC simulation on FPGAs

Design of multi-channel wireless NoC to improve on-chip communication capacity

Cross clock-domain TDM virtual circuits for networks on chips

Challenges and promises of nano and bio communication networks

Dynamic Power Management of Voltage-Frequency Island Partitioned Networks-on-Chip using Intel Sing-Chip Cloud Computer

HOPE: hotspot congestion control for Clos network on chip

Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks

All-optical wavelength-routed noc based on a novel hierarchical topology

Energy and reliability oriented mapping for regular Networks-on-Chip

Inferring packet dependencies to improve trace based simulation of on-chip networks

Link pipelining strategies for an application-specific asynchronous NoC

VLSI micro-architectures for high-radix crossbar schedulers

A software framework for trace analysis targeting multicore platforms design

Automatic verification for deadlock in Networks-on-Chips with adaptive routing and wormhole switching

Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures

Online task remapping strategies for fault-tolerant Network-on-Chip multiprocessors

Delay analysis of wormhole based heterogeneous NoC

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Interconnect physical analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for cryptographic accelerators

Reconfiguration of a 3GPP-LTE telecommunication application on a 23-core NoC-based System-on-Chip

Deadlock-free fine-grained thread migration

Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model

Reducing Network-on-Chip energy consumption through spatial locality speculation

A Comphrehensive Networks-on-Chip Simulator for Error Control Explorations

NoCs Simulation Framework for OMNeT++

Spidergon STNoC design flow

DART: a programmable architecture for NoC simulation on FPGAs

Content Provider	ACM Digital Library
Author	Wang, Danyao Jerger, Natalie Enright Steffan, J. Gregory
Abstract	The increased demand for on-chip communication bandwidth as a result of the multi-core trend has made networks on-chip (NoCs) a compelling choice for the communication backbone in next-generation systems [3]. However, NoC designs have many power, area, and performance trade-offs in topology, buffer sizes, routing algorithms and flow control mechanisms---hence the study of new NoC designs can be very time-intensive. To address this challenge we propose DART, a fast and flexible FPGA-based NoC simulation architecture. Rather than laying the NoC out in hardware on the FPGA like previous approaches [8, 6], our design virtualizes the NoC by mapping its components to a generic NoC simulation engine, composed of a fully-connected collection of fundamental components (e.g., routers and flit queues). This approach has two main advantages: (i) since FPGA implementation is decoupled it can simulate any NoC; and (ii) any NoC can be mapped to the engine without resynthe-sizing it, which can take time for a large FPGA design. We demonstrate that an implementation of DART can achieve over 100x speedup relative to a cycle-based software simulator, while maintaining the same level of simulation accuracy.
Starting Page	145
Ending Page	152
Page Count	8
File Format	PDF
ISBN	9781450307208
DOI	10.1145/1999946.1999970
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-05-01
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Simulation Fpga Network-on-chip
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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