NDLI: Efficient Generation of Energy and Performance Pareto Front for FPGA Designs (Abstract Only)

Please wait, while we are loading the content...

Physical Design Space Exploration

High-Level Design Tools for Floating Point FPGAs

Unlocking FPGAs Using High Level Synthesis Compiler Technologies

The BEEcube Story: Lessons Learned from Running a FPGA Startup for the Past 7 Years

Application of Specific Delay Window Routing for Timing Optimization in FPGA Designs

EURECA: On-Chip Configuration Generation for Effective Dynamic Data Access

Take the Highway: Design for Embedded NoCs on FPGAs

Superoptimized Memory Subsystems for Streaming Applications

Growing a Healthy FPGA Ecosystem

Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks

Mapping-Aware Constrained Scheduling for LUT-Based FPGAs

Automatic Time-Redundancy Transformation for Fault-Tolerant Circuits

Energy and Memory Efficient Mapping of Bitonic Sorting on FPGA

An Efficient and Flexible FPGA Implementation of a Face Detection System (Abstract Only)

An FPGA-Based Accelerator for the 2D Implicit FDM and Its Application to Heat Conduction Simulations (Abstract Only)

Acceleration of Synthetic Aperture Radar (SAR) Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only)

Bridging Architecture and Programming for Throughput-Oriented Vision Processing (Abstract Only)

Using Source-Level Transformations to Improve High-Level Synthesis Debug and Validation on FPGAs

Software-Driven Hardware Development

Enhancing Hardware Design Flows with MyHDL

Fine-Grained Interconnect Synthesis

Energy-Efficient Discrete Signal Processing with Field Programmable Analog Arrays (FPAAs)

Enhancements in UltraScale CLB Architecture

MATCHUP: Memory Abstractions for Heap Manipulating Programs

Wavefront Skipping using BRAMs for Conditional Algorithms on Vector Processors

Resource-Aware Throughput Optimization for High-Level Synthesis

200 MS/s ADC implemented in a FPGA employing TDCs

Ramethy: Reconfigurable Acceleration of Bisulfite Sequence Alignment

A Novel Method for Enabling FPGA Context-Switch (Abstract Only)

An FPGA Implementation of a Timing-Error Tolerant Discrete Cosine Transform (Abstract Only)

An Embedded FPGA Operating System Optimized for Vision Computing (Abstract Only)

An Automatic Design Flow for Hybrid Parallel Computing on MPSoCs (Abstract Only)

InTime: A Machine Learning Approach for Efficient Selection of FPGA CAD Tool Parameters

Rapid Prototyping of Wireless Physical Layer Modules Using Flexible Software/Hardware Design Flow

Delay-Bounded Routing for Shadow Registers

Expanding OpenFlow Capabilities with Virtualized Reconfigurable Hardware

Floating-Point DSP Block Architecture for FPGAs

Impact of Memory Architecture on FPGA Energy Consumption

On Data Forwarding in Deeply Pipelined Soft Processors

Numerical Program Optimization for High-Level Synthesis

0.5-V Highly Power-Efficient Programmable Logic using Nonvolatile Configuration Switch in BEOL

FPGA Acceleration for Simultaneous Image Reconstruction and Segmentation based on the Mumford-Shah Regularization (Abstract Only)

A Parallel And Scalable Multi-FPGA based Architecture for High Performance Applications (Abstract Only)

FPGA Implementation of Trained Coarse Carrier Frequency Offset Estimation and Correction for OFDM Signals (Abstract Only)

MedianPipes: An FPGA based Highly Pipelined and Scalable Technique for Median Filtering (Abstract Only)

RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs

Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems

System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System

Logic Gates in the routing network of FPGAs (Abstract Only)

A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only)

Energy-Efficient High-Order FIR Filtering through Reconfigurable Stochastic Processing (Abstract Only)

Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only)

Technology Mapping into General Programmable Cells

Real-Time Obstacle Avoidance for Mobile Robots via Stereoscopic Vision Using Reconfigurable Hardware (Abstract Only)

FiT: An Automated Toolkit for Matching Processor Architecture to Applications (Abstract Only)

Silicon Verification using High-Level Design Tools (Abstract Only)

Optimized Fixed-Point FPGA Implementation of SVPWM for a Two-Level Inverter (Abstract Only)

Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only)

FPGA-based BLOB Detection Using Dual-pipelining (Abstract Only)

A Hardware Implementation of a Unit for Geometric Algebra Operations With Parallel Memory Arrays (Abstract Only)

Area Optimization of Arithmetic Units by Component Sharing for FPGAs (Abstract Only)

An Automated Design Framework for Floating Point Scientific Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only)

An FPGA Implementation of Multi-stream Tracking Hardware using 2D SIMD Array (Abstract Only)

Efficient Generation of Energy and Performance Pareto Front for FPGA Designs (Abstract Only)

Customizable and High Performance Matrix Multiplication Kernel on FPGA (Abstract Only)

Sequence-based In-Circuit Breakpoints for Post-Silicon Debug (Abstract Only)

300 Thousand Gates Single Event Effect Hardened SRAM-based FPGA for Space Application (Abstract Only)

A Novel Coefficient Address Generation Algorithm for Split-Radix FFT (Abstract Only)

Accelerating Complete Decision Support Queries Through High-Level Synthesis Technology (Abstract Only)

Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only)

REPROC: A Dynamically Reconfigurable Architecture for Symmetric Cryptography (Abstract Only)

RapidPath: Accelerating Constrained Shortest Path Finding in Graphs on FPGA (Abstract Only)

FPGA Acceleration of Irregular Iterative Computations using Criticality-Aware Dataflow Optimizations (Abstract Only)

Exploring Efficiency of Ring Oscillator-Based Temperature Sensor Networks on FPGAs (Abstract Only)

Architecture of Reconfigurable-Logic Cell Array with Atom Switch: Cluster Size & Routing Fabrics (Abstract Only)

High Level Programming of Document Classification Systems for Heterogeneous Environments using OpenCL (Abstract Only)

On Implementation of LUT with Large Numbers of Inputs (Abstract Only)

Formal Verification ATPG Search Engine Emulator (Abstract Only)

A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm (Abstract Only)

Low-Resource Bluespec Design of a Modular Acquisition and Stimulation System for Neuroscience (Abstract Only)

Design of a Loeffler DCT using Xilinx Vivado HLS (Abstract Only)

Platform-Independent Gigabit Communication for Low-Cost FPGAs (Abstract Only)

A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only)

Efficient Generation of Energy and Performance Pareto Front for FPGA Designs (Abstract Only)

Content Provider	ACM Digital Library
Author	Prasanna, Viktor K. Kuppannagari, Sanmukh R.
Abstract	Analysis of trade-offs between energy efficiency and latency is essential to generate designs complying with a given set of constraints. Improvements in FPGA technologies offer a myriad choices for power and performance optimizations. Various algorithm intrinsic parameters also affect these objectives. The design space is compounded by the available choices. This requires efficient techniques to quickly explore the design space. Current techniques perform Gate/RTL level or functional level power modeling which are slow and hence not scalable. In this work we perform efficient design space exploration using a high level performance model. We develop a semi-automatic design framework to generate energy efficiency and latency trade-offs. The framework develops a performance model given a high level specification of a design with minimal user assistance. It then explores the entire design space to generate the dominating designs with respect to energy efficiency and latency metrics. We illustrate the framework using convolutional neural network which gained significance due to its application in deep learning. We simulate a few designs from the dominating set and show that the performance estimation for the dominating designs are close to the simulated results. We also show that our framework explores 6000 design points per minute on a commodity platform such as Dell workstation as opposed to state-of-the-art techniques which explore at 50 to 60 design points per minute.
Starting Page	273
Ending Page	273
Page Count	1
ISBN	9781450333153
DOI	10.1145/2684746.2689133
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-02-22
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Design framework Energy efficiency High level performance model Convolutional neural networks Design space exploration
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in