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  1. Proceedings of the 11th international conference on Architectural support for programming languages and operating systems (ASPLOS XI)
  2. Continual flow pipelines
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Programming with transactional coherence and consistency (TCC)
D-SPTF: decentralized request distribution in brick-based storage systems
HIDE: an infrastructure for efficiently protecting information leakage on the address bus
Coherence decoupling: making use of incoherence
HOIST: a system for automatically deriving static analyzers for embedded systems
Locality phase prediction
Devirtualizable virtual machines enabling general, single-node, online maintenance
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
Spatial computation
FAB: building distributed enterprise disk arrays from commodity components
Secure program execution via dynamic information flow tracking
Continual flow pipelines
Helper threads via virtual multithreading on an experimental $itanium^{®}$ 2 processor-based platform
Dynamic tracking of page miss ratio curve for memory management
Fingerprinting: bounding soft-error detection latency and bandwidth
Heat-and-run: leveraging SMT and CMP to manage power density through the operating system
An ultra low-power processor for sensor networks
Deconstructing storage arrays
Scalable selective re-execution for EDGE architectures
Low-overhead memory leak detection using adaptive statistical profiling
Compiler orchestrated prefetching via speculation and predication
Application-level checkpointing for shared memory programs
Performance directed energy management for main memory and disks
Software prefetching for mark-sweep garbage collection: hardware analysis and software redesign

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Continual flow pipelines

Content Provider ACM Digital Library
Author Gandhi, Amit Upton, Mike Srinivasan, Srikanth T. Rajwar, Ravi Akkary, Haitham
Abstract Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new challenge for processor architects. How to build a processor that provides high single-thread performance and enables multiple of these to be placed on the same die for high throughput while dynamically adapting for future applications? Conventional approaches for high single-thread performance rely on large and complex cores to sustain a large instruction window for memory tolerance, making them unsuitable for multi-core chips. We present Continual Flow Pipelines (CFP) as a new non-blocking processor pipeline architecture that achieves the performance of a large instruction window without requiring cycle-critical structures such as the scheduler and register file to be large. We show that to achieve benefits of a large instruction window, inefficiencies in management of both the scheduler and register file must be addressed, and we propose a unified solution. The non-blocking property of CFP keeps key processor structures affecting cycle time and power (scheduler, register file), and die size (second level cache) small. The memory latency-tolerant CFP core allows multiple cores on a single die while outperforming current processor cores for single-thread applications.
Starting Page 107
Ending Page 119
Page Count 13
File Format PDF
ISBN 1581138040
DOI 10.1145/1024393.1024407
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2004-10-07
Publisher Place New York
Access Restriction Subscribed
Subject Keyword Instruction window Latency tolerance Non-blocking Cfp
Content Type Text
Resource Type Article
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