NDLI: Energy-optimal caches with guaranteed lifetime

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Energy-secure computing

Write-optimized reliable design of STT MRAM

TSV array utilization in low-power 3D clock network design

ER: elastic RESET for low power and long endurance MLC based phase change memory

Industry focus session on low-power design

A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist

Power-aware performance increase via core/uncore reinforcement control for chip-multiprocessors

Panel: going green across communications and storage systems: control of power in non-mobile devices

Modeling, design and cross-layer optimization of polysilicon solar cell based micro-scale energy harvesting systems

Spin as state variable for computation: prospects and perspectives

Register file write data gating techniques and break-even analysis model

Improving energy efficiency of write-asymmetric memories by log style write

TAP: token-based adaptive power gating

Voltage droop reduction for multiple-power domain SoCs with on-die LDO using output voltage boost and adaptive response scaling

A study of the effectiveness of CPU consolidation in a virtualized multi-core server system

Advanced power and thermal management for low-power, high-performance smartphones

Ultra-low power challenges for the next generation ASIC

The core-C6 (CC6) sleep state of the AMD bobcat x86 microprocessor

Reducing L1 caches power by exploiting software semantics

High-performance low-energy STT MRAM based on balanced write scheme

Practically scalable floorplanning with voltage island generation

A dual-mode architecture for fast-switching STT-RAM

Advances in ultrabook™ platform power management

A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme

Power conversion efficiency characterization and optimization for smartphones

Static low power verification at transistor level for SoC design

A low-leakage dynamic register file with unclocked wordline and sub-segmentation for improved bitline scalability

Process variation aware data management for STT-RAM cache design

Design trade-offs for high density cross-point resistive memory

A 33μW 42 GOPS/W 64x64 pixel vision sensor with dynamic background subtraction for scene interpretation

Energy-efficient scheduling on heterogeneous multi-core architectures

Evaluation of voltage stacking for near-threshold multicore computing

DRAM power-aware rank scheduling

Design benchmarking to 7nm with FinFET predictive technology models

Thermal-aware sampling in architectural simulation

ASCIB: adaptive selection of cache indexing bits for removing conflict misses

Commercial low-power EDA tools: a review

An adaptive write word-line pulse width and voltage modulation architecture for bit-interleaved 8T SRAMs

Dynamic reconfiguration of photovoltaic energy harvesting system in hybrid electric vehicles

CCP: common case promotion for improved timing error resilience with energy efficiency

A fine-grained many $V_{T}$ design methodology for ultra low voltage operations

TapeCache: a high density, energy efficient cache based on domain wall memory

Performance and energy-efficiency improvement through modified CPL in organic transistor integrated circuits

Process and temperature invariant bandwidth and gain, low-area, low-power and high swing $G_{m}-C$ filter for multichannel neuro-potential signal conditioning

MAC: migration-aware compilation for STT-RAM based hybrid cache in embedded systems

CHARM: a composable heterogeneous accelerator-rich microprocessor

Energy-efficient GPU design with reconfigurable in-package graphics memory

Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems

An ARM perspective on addressing low-power energy-efficient SoC designs

Battery management for grid-connected PV systems with a battery

Energy-optimal caches with guaranteed lifetime

A programmable resistive power grid for post-fabrication flexibility and energy tradeoffs

A software approach for combating asymmetries of non-volatile memories

Optimal power switch design for dynamic voltage scaling from high performance to subthreshold operation

A charge pump based receiver circuit for voltage scaled interconnect

Energy-efficient signal processing in wearable embedded systems: an optimal feature selection approach

Something old and something new: P-states can borrow microarchitecture techniques too

Fan-speed-aware scheduling of data intensive jobs

Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retention

BiN: a buffer-in-NUCA scheme for accelerator-rich CMPs

0.35V, 4.1μW, 39MHz crystal oscillator in 40nm CMOS

Procedure hopping: a low overhead solution to mitigate variability in shared-L1 processor clusters

Adopting TLB index-based tagging to data caches for tag energy reduction

Static and dynamic co-optimizations for blocks mapping in hybrid caches

Design space exploration of workload-specific last-level caches

Low-power adaptive RF system design using real-time fuzzy noise-distortion control

Designing for dark silicon: a methodological perspective on energy efficient systems

HANDS: heterogeneous architectures and networks-on-chip design and simulation

XIOSim: power-performance modeling of mobile x86 cores

LogStore: toward energy-proportional storage servers

A game theoretic resource allocation for overall energy minimization in mobile cloud computing system

A low-power "near-threshold" epileptic seizure detection processor with multiple algorithm programmability

Understanding the impact of laptop power saving options on user satisfaction using physiological sensors

MultiScale: memory system DVFS with multiple memory controllers

Semantics-driven sensor configuration for energy reduction in medical sensor networks

Energy-optimal caches with guaranteed lifetime

Content Provider	ACM Digital Library
Author	Loghi, Mirko Calimera, Andrea Poncino, Massimo Mahmood, Haroon Macii, Enrico
Abstract	This work addresses the aging of the memory sub-system due to NBTI (Negative Bias Temperature Instability) in systems that have to provide a guaranteed level of service, and specifically, a guaranteed lifetime. Our approach leverages a novel cache architecture in which a smart joint use of redundancy and power management allows us to obtain caches that meet a desired lifetime target with minimal energy consumption. This is made possible by exploiting the possibility of putting the cache sub-block used for redundancy into a deep low-power state, thus allowing more energy saving than a regular architecture. Sacrificing a portion of the cache for aging mitigation only marginally affects performance thanks to the non-linear dependency of miss rate versus cache size, which allows to find the best cache size that maximizes the objective. Simulation results show that it is possible to meet the target lifetime by achieving energy reductions (measured over the lifetime of the system) ranging from 3X to 10X (2X to 8X) for a lifetime target of 15 (25) years, with marginal miss rate overhead.
Starting Page	141
Ending Page	146
Page Count	6
File Format	PDF
ISBN	9781450312493
DOI	10.1145/2333660.2333696
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-07-30
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Leakage optimization Memory hierarchy Aging Nbti
Content Type	Text
Resource Type	Article

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