NDLI: Analyzing energy friendly steady state phases of dynamic application execution in terms of sparse data structures

Please wait, while we are loading the content...

Standby power management for a 0.18μm microprocessor

$E^{2}WFQ:$ an energy efficient fair scheduling policy for wireless systems

Low-leakage asymmetric-cell SRAM

Low-power approach for decoding convolutional codes with adaptive viterbi algorithm approximations

Energy recovering static memory

Low-power color TFT LCD display for hand-held embedded systems

Fine-grain CAM-tag cache resizing using miss tags

Battery lifetime prediction for energy-aware computing

Saving energy with just in time instruction delivery

Automated selective multi-threshold design for ultra-low standby applications

Future directions in clocking multi-ghz systems

Compilers for power and energy management

Oversampled gain-boosting

TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors

Power analysis techniques for SoC with improved wiring models

Low-power VLSI decoder architectures for LDPC codes

Parametric timing and power macromodels for high level simulation of low-swing interconnects

Low-voltage memories for power-aware systems

Physical insight into fractional power dependence of saturation current on gate voltage in advanced short channel MOSFETS (alpha-power law model)

A framework for energy-scalable communication in high-density wireless networks

Managing leakage for transient data: decay and quasi-static 4T memory cells

Power-aware source routing protocol for mobile ad hoc networks

Low power integrated scan-retention mechanism

Discharge current steering for battery lifetime optimization

An adaptive serial-parallel CAM architecture for low-power cache blocks

Early evaluation techniques for low power binding

Tradeoffs in power-efficient issue queue design

$HA^{2}TSD:$ hierarchical time slack distribution for ultra-low power CMOS VLSI

±0.5V ±1.5V VHF CMOS LV/LP four-quadrant analog multiplier in modified bridged-triode scheme

A preactivating mechanism for a VT-CMOS cache using address prediction

A microarchitectural-level step-power analysis tool

A low power normalized-LMS decision feedback equalizer for a wireless packet modem

Compact models for estimating microprocessor frequency and power

Is nanoelectronics the future of microelectronics?

Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS

Contents provider-assisted dynamic voltage scaling for low energy multimedia applications

Conditional pre-charge techniques for power-efficient dual-edge clocking

Analyzing energy friendly steady state phases of dynamic application execution in terms of sparse data structures

Closed-loop adaptive voltage scaling controller for standard-cell ASICs

Towards energy-aware software-based fault tolerance in real-time systems

Reducing energy consumption of video memory by bit-width compression

Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels

Reducing transitions on memory buses using sector-based encoding technique

Runtime mechanisms for leakage current reduction in CMOS VLSI $circuits^{1,2}$

A power and resolution adaptive flash analog-to-digital converter

Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors

Power estimation of sequential circuits using hierarchical colored hardware petri net modeling

High performance and low power FIR filter design based on sharing multiplication

Efficient estimation of signal transition activity in MAC architectures

Designing SoC's

Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology

Circuit-level techniques to control gate leakage for sub-100nm CMOS

Odd/even bus invert with two-phase transfer for buses with coupling

Design of a branch-based 64-bit carry-select adder in 0.18 μm partially depleted SOI CMOS

A history-based I-cache for low-energy multimedia applications

Energy-efficient hybrid wakeup logic

Design techniques for low power high bandwidth upconversion in CMOS

Asymmetric-frequency clustering: a power-aware back-end for high-performance processors

High-level area estimation

A low-power digital matched filter for spread-spectrum systems

Novel modeling techniques for RTL power estimation

Modeling and analysis of leakage power considering within-die process variations

An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model

Retiming-based logic synthesis for low-power

Reducing access energy of on-chip data memory considering active data bitwidth

Activity-sensitive clock tree construction for low power

Analyzing energy friendly steady state phases of dynamic application execution in terms of sparse data structures

Content Provider	ACM Digital Library
Author	Daylight, E. G. Ykman-Couvreur, C. Wuytack, S. Catthoor, F.
Abstract	In the past decades, data structure analysis was mainly done at a high level of abstraction in the computer science community. For instance, choosing a linked list as a data structure as opposed to an array for a specific situation, was mainly motivated from a performance point of view under the implicit assumption that the computer platform (that had to run the software) consisted out of one monolithical, physical memory. In the context of mobile, embedded devices, energy consumption is as important as performance. In addition to this, the assumption of one monolithical memory is outdated for many (if not all) current-day platforms! Clearly, there is a need to improve the choices that are made during data structure analysis given specific knowledge of the memory hierarchy of the platform under investigation. We show how memory related energy consumption can heavily be reduced by taking into account the access behaviour of the application on the one hand and the available on-chip and off-chip memory space on the other hand. We do this by exploiting the sparseness that is present in onesteady state of the data structure under investigation. Analytical results show that energy reductions of a factor of 8.7 are feasible in comparison to common data structure implementations. We trade these gains off with on-chip memory space consumption of a custom memory architecture.
Starting Page	76
Ending Page	79
Page Count	4
File Format	PDF
ISBN	1581134754
DOI	10.1145/566408.566430
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2002-08-12
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Energy consumption Partitioned data structure On-chip memory footprint
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in