NDLI: Repartitioning and technology mapping of electronic hybrid systems

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Conference Organizing Committee

Programme Topic Chairs

Vendors Committee

Technical Programme Committee

Welcome to DATE 98

Keynote Addresses Summaries

List of Reviewers

Collapsing the transistor chain to an effective single equivalent transistor

Design of fault-secure parity-prediction booth multipliers

PASTEL: a parameterized memory characterization system

Hardware resource allocation for hardware/software partitioning in the LYCOS system

Hardware/software partitioning with integrated hardware design space exploration

Generation of interconnect topologies for communication synthesis

The design of an asynchronous VHDL synthesizer

Repartitioning and technology mapping of electronic hybrid systems

VHDL-AMS: the missing link in system design - experiments with unified modelling in automative engineering

Scheduling and module assignment for reducing BIST resources

An efficient algorithm to integrated scheduling and allocation in high-level test synthesis

RAM-based FPGA's: a test approach for the configurable logic

Novel technique for testing FPGAs

ATM traffic shaper: ATS

XFVHDL: a tool for the synthesis of fuzzy logic controllers

High speed neural network chip for trigger purposes in high energy physics

CASPER: concurrent hardware-software co-synthesis of hard real-time aperiodic and periodic specifications of embedded system architectures

Stream communication between real-time tasks in a high-performance multiprocessor

Scheduling of conditional process graphs for the synthesis of embedded systems

Model abstraction for formal verification

VHDL modelling and analysis of fault secure systems

Register transfer level VHDL models without clocks

Parallel VHDL simulation

Testing DSP cores based on self-test programs

Self-adjusting output data compression: an efficient BIST technique for RAMs

Built-in-self-test with an alternating output

From algorithms to hardware architectures: a comparison of regular and irregular structured IDCT algorithms

Smart pixel implementation of a 2-D parallel nucleic wavelet transform for mobile multimedia communications

VLSI architecture for lossless compression of medical images using the discrete wavelet transform

A model for system-level timed analysis and profiling

Efficient compilation of process-based concurrent programs without run-time scheduling

A macroscopic time and cost estimation model allowing task parallelism and hardware sharing of the codesign partitioning process

A scalable methodology for cost estimation in a transformational high-level design space exploration environment

Object-oriented modelling of parallel hardware systems

A flexible message passing mechanism for objective VHDL

Enhanced reuse and teamwork capabilities for an object-oriented extension of VHDL

Formal specification in VHDL for hardware verification

A low-redundancy approach to semi-concurrent error detection in data paths

Measuring the effectiveness of various design validation approaches for PowerPCTM microprocessor arrays

Functional scan chain testing

Design methodologies for system level IP

IP-based system-on-a-chip design

A systematic analysis of reuse strategies for design of electronic circuits

VHDL teamwork, organization units and workspace management

An object-oriented model for specification, prototyping, implementation and reuse

A flat, timing-driven design system for a high-performance CMOS processor chipset

Algorithms for detailed placement of standard cells

Timing analysis and optimization of a high-performance CMOS processor chipset

A sequential detailed router for huge grid graphs

Reconfigurable logic for systems on a chip

An energy-conscious exploration methodology for reconfigurable DSPs

Design of future systems

AFTA: a formal delay model for functional thinking analysis

Power-simulation of cell based ASICs: accuracy-and performance trade-offs

Advanced optimistic approaches in logic simulation

PSCP: a scalable parallel ASIP architecture for reactive systems

A constraint driven approach to loop pipelining and register binding

Multiple behavior module synthesis based on selective groupings

Optimal temporal partitioning and synthesis for reconfigurable architectures

An effective general connectivity concept for clustering

Improved approximation bounds for the group Steiner problem

An interactive router for analog IC design

Formal verification: a new standard CAD tool for the industrial design flow

A system-level co-verification environment for ATM hardware design

FRIDGE: a fixed-point design and simulation environment

Verification by simulation comparison using interface synthesi

Layout-driven high level synthesis for FPGA based architectures

Cross-level hierarchical high-level synthesis

An algorithm to determine mutually exclusive operations in behavioral descriptions

A performance-driven MCM router with special consideration of crosstalk reduction

Interconnect tuning strategies for high-performance ICs

A polynomial time optimal algorithm for simultaneous buffer and wire sizing

Next generation system level design tools

Estimation of the defective IDDQ caused by shorts in deep-submicron CMOS ICs

A fully digital controlled off-chip IDDQ measurement unit

March tests for word-oriented memories

A modeling approach to include mechanical microsystem components into the system simulation

Fast field solvers for thermal and electrostatic analysis

Microsystems testing: an approach and open problems

Reduced-order modeling of large linear passive multi-terminal circuits using matrix-padé approximation

An efficient algorithm for fast parasitic extraction and passive order reduction of 3D interconnect models

MCM interconnect design using two-pole approximation

Design-manufacturing interface: Part I — vision

Design-manufacturing interface: Part II - applications

Performance - manufacturability tradeoffs in IC design

Fast sequential circuit test generation using high-level and gate-level techniques

State relaxation based subsequence removal for fast static compaction in sequential circuits

Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restoration

Architectural simulation in the context of behavioral synthesis

Scheduling of outputs in grammar-based hardware synthesis of data communication protocols

Concurrent error recovery with near-zero latency in synthesized ASICs

Dynamic minimization of word-level decision diagrams

Sequential equivalence checking without state space traversal

On the reuse of symbolic simulation results for incremental equivalence verification of switch-level circuits

Silicon debug of systems-on-chips

Hierarchical characterization of analog integrated CMOS circuits

EASY - a system for computer-aided examination of analog circuits

A formal approach to verification of linear analog circuits wth parameter tolerances

Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking

Technology mapping for minimizing gate and routing area

Exploiting symbolic techniques for partial scan flip flop selection

Temperature effect on delay for low voltage applications

Data driven power optimization of sequential circuits

Gated clock routing minimizing the switched capacitance

Exact and approximate estimation for maximum instantaneous current of CMOS circuits

Embedded DRAM architectural trade-offs

Energy-delay efficient data storage and transfer architectures: circuit technology versus design methodology solutions

Hierarchical top-down design of analog sensor interfaces: from system-level specifications down to silicon

A systems theoretic approach to behavioural modeling and simulation of analog functional blocks

Switching response modeling of the CMOS inverter for sub-micron devices

On removing multiple redundancies in combinational circuits

Multi-output functional decomposition with exploitation of don't cares

An efficient divide and conquer algorithm for exact hazard free logic minimization

Restructuring logic representations with easily detectable simple disjunctive decompositions

Power estimation of behavioral descriptions

Characterization-free behavioral power modeling

Trace-driven steady-state probability estimation in FSMs with application to power estimation

Efficient verification using generalized partial order analysis

Efficient encoding schemes for symbolic analysis of petri nets

Propagation of last-transition-time constraints in gate-level timing analysis

Combinational verification based on high-level functional specifications

Switch-level fault coverage analysis for switch-capacitor systems

Optimized implementations of the multi-configuration DFT technique for analog circuits

Analog test design with IDD measurements for the detection of parametric and catastrophic faults

A new paradigm for dichotomy-based constrained encoding

A dynamic model for the state assignment problem

Efficient minarea retiming of large level-clocked circuits

IMPACT: a high-level synthesis system for low power control-flow intensive circuits

Instruction scheduling for power reduction in processor-based system design

Address bus encoding techniques for system-level power optimization

A scalable architecture for multi-threaded JAVA applications

Hardware/software co-design of a fuzzy RISC processor

Innovative system-level design environment based on FORM for transport processing system

Efficient techniques for accurate modeling and simulation of substrate coupling in mixed-signal IC's

Efficient DC fault simulation of nonlinear analog circuits

An approach to realistic fault prediction and layout design for testability in analog circuits

Synthesis of communicating controllers for concurrent hardware/software systems

A knowledge-based system for hardware-software partitioning

A formal description of VHDL-AMS analogue systems

Scanning datapaths: a fast and effective partial scan selection technique

Universal strong encryption FPGA core implementation

Data cache sizing for embedded processor applications

A programmable multi-language generator for CoDesign

Register-constrained address computation in DSP programs

Graphical entry of FSMDs revisited: putting graphical models on a solid base

AGENDA: an attribute grammar driven enviornment for the design automation of digital systems

Static analysis tools for soft-core reviews and audits

A VHDL SGRGAM model for the validation environment of a high performance graphic processor

A comparing study of technology mapping for FPGA

Fuzzy-logic digital-analogue interfaces for accurate mixed-signal simulation

Optimized timed hardware software cosimulation without roll-back

A cell and macrocell compiler for GaAs VLSI full-custom design

Architectural rule checking for high-level synthesis

A unified technique for PCB/MCM design by combining electromagnetic field analysis with circuit simulator

Core interconnect testing hazards

Quality estimation of test vectors and functional validation procedures based on fault and error models

Fault analysis in networks with concurrent error detection properties

IOCIMU - an integrated off-chip IDDQ measurement unit

Automatic topology optimization for analog module generators

Asynchronous scheduling and allocation

Path verification using Boolean satisfiability

PowerShake: a low power driven clustering and factoring methodology for Boolean expressions

Power and timing modeling for ASIC designs

Constraints space management for the layout of analog IC's

A synthesis procedure for flexible logic functions

Denotational semantics of a behavioral subset of VHDL

Correct high-level synthesis: a formal perspective

A bypass scheme for core-based system fault testing

Highly testable and compact 1-out-of-n code checker with single output

Design-for-testability for synchronous sequential circuits using locally available lines

CMOS combinational circuit sizing by stage-wise tapering

Fault detection for linear analog circuits using current injection

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