NDLI: Kicking the tires of software transactional memory: why the going gets tough

Please wait, while we are loading the content...

Utilizing shared data in chip multiprocessors with the Nahalal architecture

What can be approximated locally?: case study: dominating sets in planar graphs

Online multicast with egalitarian cost sharing

Against lock-based semantics for transactional memory

Many random walks are faster than one

Automatic data partitioning in software transactional memories

Operational analysis of processor speed scaling

Fundamental parallel algorithms for private-cache chip multiprocessors

Fast distributed scheduling via primal-dual

Kicking the tires of software transactional memory: why the going gets tough

On obstruction-free transactions

Partial snapshot objects

The adaptive transactional memory test platform: a tool for experimenting with transactional code for rock (poster)

A consistency architecture for hierarchical shared caches

Distributed packing in planar graphs

Trade-offs between the size of advice and broadcasting time in trees

A transactional approach to lock scalability

Improved distributed approximate matching

Checkpoints and continuations instead of nested transactions

A temperature-aware virtual submesh allocation scheme for noc-based manycore chips

Cache-efficient dynamic programming algorithms for multicores

A primal-dual resource augmentation analysis of a constant approximate algorithm for stable coalitions in a cluster

RingSTM: scalable transactions with a single atomic instruction

Practical weak-atomicity semantics for java stm

Communication in wireless networks with directional antennas

Improving software concurrency with hardware-assisted memory snapshot

Combinable memory-block transactions

Polylogarithmic network navigability using compact metrics with small stretch

Cost sharing mechanisms for near-optimal traffic aggregation and network design

RaceTM: detecting data races using transactional memory

Graph partitioning into isolated, high conductance clusters: theory, computation and applications to preconditioning

Adaptive transaction scheduling for transactional memory systems

Optimal speedup on a low-degree multi-core parallel architecture (LoPRAM)

Scheduling strategies for optimistic parallel execution of irregular programs

Improved approximations for multiprocessor scheduling under uncertainty

Irrevocable transactions and their applications

Commit phase in timestamp-based stm

Tight competitive ratios for parallel disk prefetching and caching

Distributed voronoi diagram computation in wireless sensor networks

Parallelizing dynamic information flow tracking

On spreading recommendations via social gossip

A first insight into object-aware hardware transactional memory

Finding strongly connected components in parallel using $O(log^{2}n)$ reachability queries

Energy-optimal distributed algorithms for minimum spanning trees

Competitive non-migratory scheduling for flow time and energy

Dreadlocks: efficient deadlock detection

Directed transmission method, a fully asynchronous approach to solve sparse linear systems in parallel

Safe open-nested transactions through ownership

Data replication in p2p environments

Ased: availability, security, and debugging support usingtransactional memory

Leveraging non-blocking collective communication in high-performance applications

Graphical congestion games with linear latencies

Fractal communication in software data dependency graphs

Kicking the tires of software transactional memory: why the going gets tough

Content Provider	ACM Digital Library
Author	Welc, Adam Saha, Bratin Adl-Tabatabai, Ali-Reza Lee, Hsien-Hsin S. Yoo, Richard M. Ni, Yang
Abstract	Transactional Memory (TM) promises to simplify concurrent programming, which has been notoriously difficult but crucial in realizing the performance benefit of multi-core processors. Software Transaction Memory (STM), in particular, represents a body of important TM technologies since it provides a mechanism to run transactional programs when hardware TM support is not available, or when hardware TM resources are exhausted. Nonetheless, most previous researches on STMs were constrained to executing trivial, small-scale workloads. The assumption was that the same techniques applied to small-scale workloads could readily be applied to real-life, large-scale workloads. However, by executing several nontrivial workloads such as particle dynamics simulation and game physics engine on a state of the art STM, we noticed that this assumption does not hold. Specifically, we identified four major performance bottlenecks that were unique to the case of executing large-scale workloads on an STM: false conflicts, over-instrumentation, privatization-safety cost, and poor amortization. We believe that these bottlenecks would be common for any STM targeting real-world applications. In this paper, we describe those identified bottlenecks in detail, and we propose novel solutions to alleviate the issues. We also thoroughly validate these approaches with experimental results on real machines.
Starting Page	265
Ending Page	274
Page Count	10
File Format	PDF
ISBN	9781595939739
DOI	10.1145/1378533.1378582
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-06-01
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Measurement C/c++ Compiler Runtime Software transactional memory Performance
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in