NDLI: Modulo scheduling for highly customized datapaths to increase hardware reusability

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Modulo scheduling for highly customized datapaths to increase hardware reusability

Content Provider	ACM Digital Library
Author	Mahlke, S ott Fan, Kevin Kudlur, Manjunath Park, Hyun hul
Abstract	In the embedded domain, custom hardware in the form of ASICs is often used to implement critical parts of applications when performance and energy efficiency goals cannot be met with software implementations on a general purpose processor or DSP. The downsides of using ASICs include high non-recurring engineering costs, inability to accommodate changes in the application after production, and inability to reuse hardware for new applications. However, by allowing a degree of post-programmability, the hardware can retain high performance and energy efficiency while increasing flexibility and reusability. The difficulty with programmable custom hardware lies in mapping new applications onto an existing datapath that is both sparse and irregular. This paper proposes a constraint-driven modulo scheduler that maps software-pipelineable loops onto programmable loop accelerator hardware. The scheduler is able to target accelerators with widely varying levels of datapath functional capability and connectivity, and thus, varying degrees of programmability. The paper investigates the ability of the scheduler to map new loops onto existing hardware, which depends on both the degree of programmability of the hardware as well as the similarity of the new loop to the original loop for which the hardware was designed.
Starting Page	124
Ending Page	133
Page Count	10
File Format	PDF
ISBN	9781595939784
DOI	10.1145/1356058.1356075
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-04-06
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Loop accelerator Modulo scheduling Programmable asic
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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