NDLI: A true hardware read barrier

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A true hardware read barrier

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A true hardware read barrier

Content Provider	ACM Digital Library
Author	Meyer, Matthias
Abstract	Read barriers synchronize compacting garbage collection and application processing in a simple yet elegant way. Unfortunately, read barrier checks are expensive to implement in software, and even with hardware support, the clustering of read barrier faults irregularly impairs application progress to an unacceptable extent. For this reason, read barriers are often considered unsuitable for hard real-time systems.In this paper, we introduce a novel hardware read barrier design for an object-based RISC architecture. The design integrates read barrier checking and, for the first time, read barrier fault handling directly into a processor pipeline.Our system handles read barrier faults within 20 clock cycles on average. Despite fault clustering, all application programs we have run on our prototype show minimum mutator utilizations of more that 55% within arbitrary time intervals of only 1ms. Thanks to this property, our system facilitates worst case estimates for tasks with very short response times, thereby paving the way for garbage collection in embedded systems with extremely fine-grained real-time requirements.
Starting Page	3
Ending Page	16
Page Count	14
File Format	PDF
ISBN	1595932216
DOI	10.1145/1133956.1133959
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-06-10
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Real-time garbage collection Hardware support Read barrier Object-based processor architecture
Content Type	Text
Resource Type	Article

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