NDLI: Soft errors: the hardware-software interface

Please wait, while we are loading the content...

Wireless innovations for smartphones

Internet-of-energy: combining embedded computing and communication for the smart grid

Lifetime improvement through runtime wear-based task mapping

Dynamic transient fault detection and recovery for embedded processor datapaths

Automatic extraction of multi-objective aware pipeline parallelism using genetic algorithms

A distributed interleaving scheme for efficient access to WideIO DRAM memory

HyCoS: hybrid compiled simulation of embedded software with target dependent code

A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture

Dynamic property mining for embedded software

Synthesis of custom networks of heterogeneous processing elements for complex physical system emulation

Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores

BPR: fast FPGA placement and routing using macroblocks

Testbenches for advanced TLM verification

DevScope: a nonintrusive and online power analysis tool for smartphone hardware components

Concurrent architecture and schedule optimization of time-triggered automotive systems

Fast online synthesis of generally programmable digital microfluidic biochips

Enabling ultra-low power operation in high-end wireless sensor networks nodes

Worst-case throughput analysis of real-time dynamic streaming applications

Working-set-based address mapping for ultra-large-scaled flash devices

An exploration methodology for a customizable OpenCL stereo-matching application targeted to an industrial multi-cluster architecture

A MDD methodology for specification of embedded systems and automatic generation of fast configurable and executable performance models

Hands-on tutorial: coarse-grained reconfigurable architectures - compilation and exploration

Computing without processors

Trends in automotive embedded systems

A real-time, energy-efficient system software suite for heterogeneous multicore platforms

SPI-SNOOPER: a hardware-software approach for transparent network monitoring in wireless sensor networks

Managing latency in embedded streaming applications under hard-real-time scheduling

Minimizing power supply noise through harmonic mappings in networks-on-chip

Fast simulation of systems embedding VLIW processors

The roce-bush router: a case for routing-centric dimensional decomposition for low-latency 3D noC routers

Efficient self-learning techniques for SAT-based test generation

Knowledge-based design space exploration of wireless sensor networks

COOL: control-based optimization of load-balancing for thermal behavior

Generating interlocked instruction pipelines from specifications of instruction sets

SystemC as completing pillar in industrial OVM based verification environments

ADEL: an automatic detector of energy leaks for smartphone applications

A SAFE approach towards early design space exploration of fault-tolerant multimedia MPSoCs

An intelligent compaction technique for pin constrained routing in cross referencing digital microfluidic biochips

Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions

Synthesis of communication schedules for TTEthernet-based mixed-criticality systems

A case of system-level hardware/software co-design and co-verification of a commodity multi-processor system with custom hardware

Software energy optimization through fine-grained function-level voltage and frequency scaling

Soft errors: the hardware-software interface

A standards-based, fully-open software platform for smart embedded systems

Research issues in smart phones, notepads and related services

ViPZonE: OS-level memory variability-driven physical address zoning for energy savings

A novel NoC-based design for fault-tolerance of last-level caches in CMPs

Dynamic scheduling of stream programs on embedded multi-core processors

Worst-case performance analysis of 2-D mesh NoCs using multi-path minimal routing

DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs

Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs

Using static analysis for coverage extraction fromemulation/prototyping platforms

Spatially- and temporally-adaptive communication protocols for zero-maintenance sensor networks relying on opportunistic energy scavenging

Adaptive online heuristic performance estimation and power optimization for reconfigurable embedded systems

Designing parameterized signal processing ips for high level synthesis in a model based design environment

The system verification methodology for advanced TLM verification

Don't burn your mobile!: safe computational re-sprinting via model predictive control

Synthesis of optimized hardware transactors from abstract communication specifications

LRCG: latch-based random clock-gating for preventing power analysis side-channel attacks

A hierarchical control scheme for energy quota distribution in hybrid distributed video coding

A configurable test infrastructure using a mixed-language and mixed-level IP integration IP-XACT flow

From RTL IP to functional system-level models with extra-functional properties

Generation of TLM testbenches using mutation testing

Run-time resource management based on design space exploration

A testbench specification language for SystemC verification

Network-aware design-space exploration of a power-efficient embedded application

SystemC simulation on GP-GPUs: CUDA vs. OpenCL

Soft errors: the hardware-software interface

Content Provider	ACM Digital Library
Author	Lee, Kyoungwoo Shrivastava, Aviral Jeyapaul, Reiley
Abstract	A recent report from the ITRS identifies soft errors, as one of the most important reliability challenges for the coming decades. Soft errors are transient errors caused by several effects e.g., voltage fluctuations, wire-cross talks, and cosmic particle strikes; and manifest as a temporary switch of the logic value of a transistor. While it is not possible to prove nor disprove that a certain error happened due to soft errors, several fiscal disasters e.g., Sun server crashes in 2000, and HP server crashes in 2005, have been attributed to soft errors. Industry has moved from the position of ignoring soft errors to adding design efforts for protection from them. For instance, in the recently announced nVIDIA's Fermi GPUs, the L1 cache, L2 cache and register files are ECC protected. Although the soft error rate is about once-per year today, it is expected to reach alarming levels of once-per-day in about a decade or two. Researchers are busy finding cost-effective solutions to protect computing devices from soft errors. This tutorial will attempt to cover the entire gamut of soft error protection techniques, but will particularly focus on the soft error mitigation techniques at the hardware/software interface. Much time will be spent on microarchitectural, compiler, and hybrid compiler-microarchitectural techniques for soft error mitigation. This tutorial will be particularly useful for budding researchers who are fascinated by soft errors, and want to explore this as their research direction. For such researchers, this tutorial will be a one-stop-shop to acquire knowledge of and analyze seminal research work in the field of soft error mitigation, at several design layers. For developers who have been working on soft errors at different levels, this will give them a picture of what can be done at other levels, so that they can provide complementary cross-layer protection. Finally, researchers and developers working on other aspects of system design can learn how soft errors are going to affect them.
Starting Page	577
Ending Page	578
Page Count	2
File Format	PDF
ISBN	9781450314268
DOI	10.1145/2380445.2380534
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-10-07
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Compiler Microarchitectural techniques Soft error mitigation
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in