NDLI: Reducing control overhead in dataflow architectures

Please wait, while we are loading the content...

Architectural support for operating system-driven CMP cache management

Compiling for stream processing

Self-checking instructions: reducing instruction redundancy for concurrent error detection

Wavelet-based phase classification

Hardware support for spin management in overcommitted virtual machines

DEP: detailed execution profile

Reducing control overhead in dataflow architectures

Two-level mapping based cache index selection for packet forwarding engines

Adaptive reorder buffers for SMT processors

Overlapping dependent loads with addressless preload

Experiences with MapReduce, an abstraction for large-scale computation

Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource

Region array SSA

A low-cost memory remapping scheme for address bus protection

Complexity-based program phase analysis and classification

Testing implementations of transactional memory

Whole-program optimization of global variable layout

Power-efficient instruction delivery through trace reuse

Program generation for the all-pairs shortest path problem

SEED: scalable, efficient enforcement of dependences

Prematerialization: reducing register pressure for free

Challenges and opportunities in the post single-thread-processor era

Core architecture optimization for heterogeneous chip multiprocessors

A two-phase escape analysis for parallel java programs

Efficient data protection for distributed shared memory multiprocessors

Performance prediction based on inherent program similarity

Efficient emulation of hardware prefetchers via event-driven helper threading

Fast, automatic, procedure-level performance tuning

Branch predictor guided instruction decoding

Combining analytical and empirical approaches in tuning matrix transposition

SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency

An empirical evaluation of chains of recurrences for array dependence testing

Deep computing in biology: challenges and progress

Processor architecture: too much parallelism?

Reducing control overhead in dataflow architectures

Content Provider	ACM Digital Library
Author	Oskin, Mark Eggers, Susan Swanson, Steve Petersen, Andrew Mercaldi, Martha Schwerin, Andrew Putnam, Andrew
Abstract	In recent years, computer architects have proposed tiled architectures in response to several emerging problems in processor design, such as design complexity, wire delay, and fabrication reliability. One of these architectures, WaveScalar, uses a dynamic, tagged-token dataflow execution model to simplify the design of the processor tiles and their interconnection network and to achieve good parallel performance. However, using a dataflow execution model reawakens old problems, including the instruction overhead required for control flow. Previous work compiling the functional language Id to the Monsoon Dataflow System found this overhead to be 2–3× that of programs written in C and targeted to a MIPS R3000.In this paper, we present and analyze three compiler optimizations that significantly reduce control overhead with minimal additional hardware. We begin by describing how to translate imperative code into dataflow assembly and analyze the resulting control overhead. We report a similar 2–4× instruction overhead, which suggests that the execution model, rather than a specific source language or target architecture, is responsible. Then, we present the compiler optimizations, each of which is designed to eliminate a particular type of control overhead, and analyze the extent to which they were able to do so. Finally, we evaluate the effect using all optimizations together has on program performance. Together, the optimizations reduce control overhead by 80% on average, increasing application performance between 21–37%.
Starting Page	182
Ending Page	191
Page Count	10
File Format	PDF
ISBN	159593264X
DOI	10.1145/1152154.1152184
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-09-16
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Compiler Wavescalar Tiled architecture Dataflow
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Area-Performance Trade-offs in Tiled Dataflow Architectures

Area-Performance Trade-offs in Tiled Dataflow Architectures

Reducing control overhead in dataflow architectures (2006)

Area-Performance Trade-offs in Tiled Dataflow Architectures

Instruction scheduling for a tiled dataflow architecture

Designing real-time H.264 decoders with dataflow architectures

Designing real-time H.264 decoders with dataflow architectures

Instruction scheduling for a tiled dataflow architecture (CARN, Vol. 34, Issue. 5)

The WaveScalar architecture

Reducing control overhead in dataflow architectures

Similar Documents

Area-Performance Trade-offs in Tiled Dataflow Architectures

Area-Performance Trade-offs in Tiled Dataflow Architectures

Reducing control overhead in dataflow architectures (2006)

Area-Performance Trade-offs in Tiled Dataflow Architectures

Instruction scheduling for a tiled dataflow architecture

Designing real-time H.264 decoders with dataflow architectures

Designing real-time H.264 decoders with dataflow architectures

Instruction scheduling for a tiled dataflow architecture (CARN, Vol. 34, Issue. 5)

The WaveScalar architecture

Reducing control overhead in dataflow architectures