NDLI: Swift: a register-based JIT compiler for embedded JVMs

Please wait, while we are loading the content...

Challenges in building a real, large private cloud

Modeling virtualized applications using machine learning techniques

Virtualization challenges: a view from server consolidation perspective

SimTester: a controllable and observable testing framework for embedded systems

Enhancing TCP throughput of highly available virtual machines via speculative communication

libdft: practical dynamic data flow tracking for commodity systems

DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support

Block storage virtualization with commodity secure digital cards

REEact: a customizable virtual execution manager for multicore platforms

Swift: a register-based JIT compiler for embedded JVMs

SecondSite: disaster tolerance as a service

Transparent dynamic instrumentation

Adding dynamically-typed language support to a statically-typed language compiler: performance evaluation, analysis, and tradeoffs

Replacement attacks against VM-protected applications

DVM: towards a datacenter-scale virtual machine

Facilitating inter-application interactions for OS-level virtualization

CompSC: live migration with pass-through devices

Execution mining

Unpicking the knot: teasing apart VM/application interdependencies

Protecting applications against TOCTTOU races by user-space caching of file metadata

V2E: combining hardware virtualization and softwareemulation for transparent and extensible malware analysis

Swift: a register-based JIT compiler for embedded JVMs

Content Provider	ACM Digital Library
Author	Yang, Zhemin Zang, Binyu Yang, Min Zhang, Yuan Zhou, Bo Zhang, Weihua
Abstract	Code quality and compilation speed are two challenges to JIT compilers, while selective compilation is commonly used to trade-off these two issues. Meanwhile, with more and more Java applications running in mobile devices, selective compilation meets many problems. Since these applications always have flat execution profile and short live time, a lightweight JIT technique without losing code quality is extremely needed. However, the overhead of compiling stack-based Java bytecode to heterogeneous register-based machine code is significant in embedded devices. This paper presents a fast and effective JIT technique for mobile devices, building on a register-based Java bytecode format which is more similar to the underlying machine architecture. Through a comprehensive study on the characteristics of Java applications, we observe that virtual registers used by more than 90% Java methods can be directly fulfilled by 11 physical registers. Based on this observation, this paper proposes Swift, a novel JIT compiler on register-based bytecode, which generates native code for RISC machines. After mapping virtual registers to physical registers, the code is generated efficiently by looking up a translation table. And the code quality is guaranteed by the static compiler which is used to generate register-based bytecode. Besides, we design two lightweight optimizations and an efficient code unloader to make Swift more suitable for embedded environment. As the prevalence of Android, a prototype of Swift is implemented upon DEX bytecode which is the official distribution format of Android applications. Swift is evaluated with three benchmarks (SPECjvm98, EmbeddedCaffeineMark3 and JemBench2) on two different ARM SOCs: S3C6410 (armv6) and OMAP3530 (armv7). The results show that Swift achieves a speedup of 3.13 over the best-performing interpreter on the selected benchmarks. Compared with the state-of-the-art JIT compiler in Android, JITC-Droid, Swift achieves a speedup of 1.42.
Starting Page	63
Ending Page	74
Page Count	12
File Format	PDF
ISBN	9781450311762
DOI	10.1145/2151024.2151035
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-03-03
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Register-based bytecode Embedded jvm Just-in-time compiler Android
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in