NDLI: Domain-specific models for innovation in analytics

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Internet of mobile things: challenges and opportunities

Virtues and limitations of commodity hardware transactional memory

ATCache: reducing DRAM cache latency via a small SRAM tag cache

What is the cost of weak determinism?

Versatile and scalable parallel histogram construction

Adaptive heterogeneous scheduling for integrated GPUs

Invyswell: a hybrid transactional memory for haswell's restricted transactional memory

PATS: pattern aware scheduling and power gating for GPGPUs

Realm: an event-based low-level runtime for distributed memory architectures

Domain-specific models for innovation in analytics

OpenTuner: an extensible framework for program autotuning

Memory scheduling towards high-throughput cooperative heterogeneous computing

Trading cache hit rate for memory performance

PEMOGEN: automatic adaptive performance modeling during program runtime

$D^{2}MA:$ accelerating coarse-grained data transfer for GPUs

Automatic execution of single-GPU computations across multiple GPUs

An Event-Based Language for Dynamic Binary Translation Frame Works

Cooperative cache scrubbing

SpongeDirectory: flexible sparse directories utilizing multi-level memristors

ILP and TLP in shared memory applications: a limit study

Bitwise data parallelism in regular expression matching

Warp-aware trace scheduling for GPUs

Consolidated conflict detection for hardware transactional memory

Heterogeneous microarchitectures trump voltage scaling for low-power cores

kMAF: automatic kernel-level management of thread and data affinity

Velociraptor: an embedded compiler toolkit for numerical programs targeting CPUs and GPUs

Bounded memory scheduling of dynamic task graphs

Compiler support for selective page migration in NUMA architectures

ArrayTool: a lightweight profiler to guide array regrouping

VAST: the illusion of a large memory space for GPUs

LCA: a memory link and cache-aware co-scheduling approach for CMPs

Improving Performance of Streaming Applications with Filtering and Control Messages

KLA: a new algorithmic paradigm for parallel graph computations

EFetch: optimizing instruction fetch for event-driven webapplications

CAWS: criticality-aware warp scheduling for GPGPU workloads

DeSTM: harnessing determinism in STMs for application development

RCS: runtime resource and core scaling for power-constrained multi-core processors

Shuffling: a framework for lock contention aware thread scheduling for multicore multiprocessor systems

COLORIS: a dynamic cache partitioning system using page coloring

Design for scalability in enterprise SSDs

Automatic optimization of thread-coarsening for graphics processors

A run-time power manager exploiting software parallelism

Stratified Sampling for Even Workload Partitioning

Tiling and optimizing time-iterated computations on periodic domains

XStream: cross-core spatial streaming based MLC prefetchers for parallel applications in CMPs

Graph-based performance accounting for chip multiprocessor memory systems

Design of a Hybrid MPI-CUDA Benchmark Suite for CPU-GPU Clusters

SQRL: hardware accelerator for collecting software data structures

Data Remapping for an Energy Efficient Burst Chop in DRAM Memory Systems

Optimizing stencil code via locality of computation

Data-reuse Optimizations for pipelined Tiling with Parametric Tile Sizes

ADHA: automatic data layout framework for heterogeneous architectures

From Petascale to the Pocket: Adaptively Scaling Parallel Programs for Mobile SoCs

Active learning accelerated automatic heuristic construction for parallel program mapping

Coarrays in GNU Fortran

Preemptive thread block scheduling with online structural runtime prediction for concurrent GPGPU kernels

Locality-Aware Memory Association for Multi-Target Worksharing in OpenMP

Using STT-RAM to enable energy-efficient near-threshold chip multiprocessors

Processing Big Data Graphs on Memory-Restricted Systems

Protection and utilization in shared cache through rationing

Automatic parallelism through macro dataflow in high-level array languages

A runtime support mechanism for fast mode switching of a self-morphing core for power efficiency

Rollback-free value prediction with approximate loads

Measuring flexibility in single-ISA heterogeneous processors

SM-centric transformation: circumventing hardware restrictions for flexible GPU scheduling

Domain-specific models for innovation in analytics

Content Provider	ACM Digital Library
Author	Blainey, Bob
Abstract	Big data is a transformational force for businesses and organizations of every stripe. The ability to rapidly and accurately derive insights from massive amounts of data is becoming a critical competitive differentiator so it is driving continuous innovation among business analysts, data scientists, and computer engineers. Two of the most important success factors for analytic techniques are the ability to quickly develop and incrementally evolve them to suit changing business needs and the ability to scale these techniques using parallel computing to process huge collections of data. Unfortunately, these goals are often at odds with each other because innovation at the algorithm and data model level requires a combination of domain knowledge and expertise in data analysis while achieving high scale demands expertise in parallel computing, cloud computing and even hardware acceleration. In this talk, I will examine various approaches to bridging these two goals, with a focus on domain-specific models which simultaneously improve the agility of analytics development and the achievement of efficient parallel scaling.
Starting Page	301
Ending Page	302
Page Count	2
File Format	PDF
ISBN	9781450328098
DOI	10.1145/2628071.2635932
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-08-24
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Domain-specific models Parallel computing Application development Parallel scaling Analytics
Content Type	Text
Resource Type	Article

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