NDLI: Multi-DaC programming model: a variant of multi-BSP model for divide-and-conquer algorithms

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Multi-DaC programming model: a variant of multi-BSP model for divide-and-conquer algorithms

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Multi-DaC programming model: a variant of multi-BSP model for divide-and-conquer algorithms

Content Provider	ACM Digital Library
Author	Savadi, Abdorreza Deldari, Hossein Moradi, Morteza
Abstract	Nowadays, the evolution of multi-core architectures goes towards increasing the number of cores and levels of cache. Meanwhile, current typical parallel programming models are unable to exploit the potential of these processors efficiently. In order to achieve desired performance on these hardwares we need to understand architectural parameters appropriately and also apply them in algorithm design. Computational models such as Multi-BSP, illustrate these parameters and explain adequate methods for designing algorithms on multi-cores. One of the most applicable categories of problems is Divide-and-Conquer (DaC) that needs to be adapted by such model for implementing on these systems. In this paper, we have attempted to make a mapping between DaC tree and the Memory Hierarchy (MH) of multi-core processor. Multi-BSP model inspired us to introduce Multi-DaC programming model. Analogous to Multi-BSP analysis, lower bounds for communication and synchronization costs have been presented in the paper respecting DaC algorithms. This work is a step towards making multi-core programming easy and tries to obtain correct analysis of DaC algorithm behavior on multi-core architectures.
Starting Page	41
Ending Page	46
Page Count	6
File Format	PDF
ISBN	9781450311175
DOI	10.1145/2103736.2103743
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-01-28
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Multi-core architectures Memory hierarchy Multi-bsp Divide-and-conquer Parallel Cache
Content Type	Text
Resource Type	Article

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