NDLI: A physical-location-aware fault redistribution for maximum IR-drop reduction

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Analog circuit verification by statistical model checking

FSM model abstraction for analog/mixed-signal circuits by learning from I/O trajectories

A structured parallel periodic arnoldi shooting algorithm for RF-PSS analysis based on GPU platforms

Hierarchical exact symbolic analysis of large analog integrated circuits by symbolic stamps

Geometry variations analysis of $TiO_{2}$ thin-film and spintronic memristors

AdaMS: adaptive MLC/SLC phase-change memory design for file storage

System accuracy estimation of SRAM-based device authentication

On-chip hybrid power supply system for wireless sensor nodes

A moment-matching scheme for the passivity-preserving model order reduction of indefinite descriptor systems with possible polynomial parts

Balanced truncation for time-delay systems via approximate Gramians

Efficient sensitivity-based capacitance modeling for systematic and random geometric variations

Parallel statistical capacitance extraction of on-chip interconnects with an improved geometric variation model

A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video

A gate-level pipelined 2.97GHz self synchronous FPGA in 65nm CMOS

A 4.32 $mm^{2}$ 170mW LDPC decoder in 0.13μm CMOS for WiMax/Wi-Fi applications

All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter

Jitter amplifier for oscillator-based true random number generator

A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles

Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism

Geyser-2: the second prototype CPU with fine-grained run-time power gating

An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture

Design and chip implementation of a heterogeneous multi-core DSP

A low-power management technique for high-performance domino circuits

Design and evaluation of variable stages pipeline processor chip

TurboVG: a HW/SW co-designed multi-core openVG accelerator for vector graphics applications with embedded power profiler

Design and implementation of a high performance closed-loop MIMO communications with ultra low complexity handset

A 58-63.6GHz quadrature PLL frequency synthesizer using dual-injection technique

An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generation

A 32Gbps low propagation delay 4x4 switch IC for feedback-based system in 0.13μm CMOS technology

A fully integrated shock wave transmitter with an on-chip dipole antenna for pulse beam-formability in 0.18-μm CMOS

An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS

Robust and efficient baseband receiver design for MB-OFDM UWB system

A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder

A 80-400 MHz 74 dB-DR Gm-C low-pass filter with a unique auto-tuning system

An adaptively biased low-dropout regulator with transient enhancement

A low-power triple-mode sigma-delta DAC for reconfigurable (WCDMA/TD-SCDMA/GSM) transmitters

A simple non-coherent solution to the UWB-IR communication

Thermally optimal stop-go scheduling of task graphs with real-time constraints

Register allocation for write activity minimization on non-volatile main memory

Leakage conscious DVS scheduling for peak temperature minimization

Reconfiguration-aware real-time scheduling under QoS constraint

Template-based memory access engine for accelerators in SoCs

Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems

Network-on-chip router design with buffer-stealing

Minimizing buffer requirements for throughput constrained parallel execution of synchronous dataflow graph

A fast approximation technique for power grid analysis

Equivalent lumped element models for various n-port through silicon vias networks

Clock tree optimization for electromagnetic compatibility (EMC)

Pulser gating: a clock gating of pulsed-latch circuits

Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC

Emerging sensing techniques for emerging memories

A frequent-value based PRAM memory architecture

Two-terminal resistive switches (memristors) for memory and logic applications

Co-design of cyber-physical systems via controllers with flexible delay constraints

Enhanced heterogeneous code cache management scheme for dynamic binary translation

Fast hybrid simulation for accurate decoded video quality assessment on MPSoC platforms with resource constraints

On the interplay of loop caching, code compression, and cache configuration

Path criticality computation in parameterized statistical timing analysis

Run-time adaptable on-chip thermal triggers

Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs

The impact of inverse narrow width effect on sub-threshold device sizing

Post-silicon bug detection for variation induced electrical bugs

Diagnosis-assisted supply voltage configuration to increase performance yield of cell-based designs

Run-time adaptive performance compensation using on-chip sensors

The alarms project: a hardware/software approach to addressing parameter variations

Automatic formal verification of reconfigurable DSPs

SoC HW/SW verification and validation

Utilizing high level design information to speed up post-silicon debugging

From RTL to silicon: the case for automated debug

Multi-core parallel simulation of system-level description languages

Variation-aware logic mapping for crossbar nano-architectures

Routing with graphene nanoribbons

ILP-based inter-die routing for 3D ICs

CELONCEL: effective design technique for 3-D monolithic integration targeting high performance integrated circuits

OPAL: a multi-layer hybrid photonic NoC for 3D ICs

Enabling quality-of-service in nanophotonic network-on-chip

Vertical interconnects squeezing in symmetric 3D mesh network-on-chip

Power-efficient tree-based multicast support for networks-on-chip

Area-efficient FPGA logic elements: architecture and synthesis

Selectively patterned masks: structured ASIC with asymptotically ASIC performance

A robust ECO engine by resource-constraint-aware technology mapping and incremental routing optimization

SETmap: a soft error tolerant mapping algorithm for FPGA designs with low power

All-out fight against yield losses by design-manufacturing collaboration in nano-lithography era

EUV lithography: prospects and challenges

Future electron-beam lithography and implications on design and CAD tools

Exploration of VLSI CAD researches for early design rule evaluation

Handling dynamic frequency changes in statically scheduled cycle-accurate simulation

Coarse-grained simulation method for performance evaluation of a shared memory system

T-SPaCS: a two-level single-pass cache simulation methodology

Fast data-cache modeling for native co-simulation

On the design and analysis of fault tolerant NoC architecture using spare routers

A resilient on-chip router design through data path salvaging

NS-FTR: a fault tolerant routing scheme for networks on chip with permanent and runtime intermittent faults

A thermal-aware application specific routing algorithm for network-on-chip design

An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits

Register pressure aware scheduling for high level synthesis

Parallel cross-layer optimization of high-level synthesis and physical design

Network flow-based simultaneous retiming and slack budgeting for low power design

Managing complexity in design debugging with sequential abstraction and refinement

Facilitating unreachable code diagnosis and debugging

Deterministic test for the reproduction and detection of board-level functional failures

Equivalence checking of scheduling with speculative code transformations in high-level synthesis

An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs

On applying erroneous clock gating conditions to further cut down power

Low power discrete voltage assignment under clock skew scheduling

A practical method for multi-domain clock skew optimization

Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree construction

Cut-demand based routing resource allocation and consolidation for routability enhancement

Negotiation-based layer assignment for via count and via overflow minimization

Wire synthesizable global routing for timing closure

Biological information sensing technologies for medical, health care, and wellness applications

Ultra-low power microcontrollers for portable, wearable, and implantable medical electronics

Human++: wireless autonomous sensor technology for body area networks

Healthcare of an organization: using wearable sensors and feedback system for energizing workers

A polynomial-time custom instruction identification algorithm based on dynamic programming

Exploring the fidelity-efficiency design space using imprecise arithmetic

Throughput optimization for latency-insensitive system with minimal queue insertion

A fast and effective dynamic trace-based method for analyzing architectural performance

Controlling NBTI degradation during static burn-in testing

A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs

NBTI-aware power gating design

Robust power gating reactivation by dynamic wakeup sequence throttling

Robust clock tree synthesis with timing yield optimization for 3D-ICs

Track routing optimizing timing and yield

Simultaneous redundant via insertion and line end extension for yield optimization

Pruning-based trace signal selection algorithm

Temporal and spatial isolation in a virtualization layer for multi-core processor based information appliances

Mathematical limits of parallel computation for embedded systems

An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAs

Power management strategies in data transmission

Robust spatial correlation extraction with limited sample via L1-norm penalty

Device-parameter estimation with on-chip variation sensors considering random variability

Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliability

Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic light emitting diode displays

A physical-location-aware fault redistribution for maximum IR-drop reduction

On the impact of gate oxide degradation on SRAM dynamic and static write-ability

A self-testing and calibration method for embedded successive approximation register ADC

On-chip dynamic signal sequence slicing for efficient post-silicon debugging

AVS-aware power-gate sizing for maximum performance and power efficiency of power-constrained processors

Energy/reliability trade-offs in fault-tolerant event-triggered distributed embedded systems

Profile assisted online system-level performance and power estimation for dynamic reconfigurable embedded systems

Battery-aware task scheduling in distributed mobile systems with lifetime constraint

Advanced system LSIs for home 3D system

Development of low power and high performance application processor (T6G) for multimedia mobile applications

Design constraint of fine grain supply voltage control LSI

FPGA prototyping using behavioral synthesis for improving video processing algorithm and FHD TV SoC design

An RTL-to-GDS2 design methodology for advanced system LSI

High performance lithographic hotspot detection using hierarchically refined machine learning

Rapid layout pattern classification

Mask cost reduction with circuit performance consideration for self-aligned double patterning

Post-routing layer assignment for double patterning

Fault simulation and test generation for clock delay faults

Compression-aware capture power reduction for at-speed testing

Fault diagnosis aware ATE assisted test response compaction

Secure scan design using shift register equivalents against differential behavior attack

An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designs

An integer programming placement approach to FPGA clock power reduction

Row-based area-array I/O design planning in concurrent chip-package design flow

A provably good approximation algorithm for rectangle escape problem with application to PCB routing

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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