NDLI: A methodology for guided behavioral-level optimization

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General Chair's Welcome

Executive Committee

Technical Program Committee

1998 Best Paper Award

ACSEE Undergraduate Scholarships

1998 IEEE Fellows

SIGDA Meritorious Service Award

Design Automation Conference Graduate Scholarship Awards

36th Call for Papers

Opening Keynote Address-William J. Spencer

Thursday Keynote Address-George H. Heilmeier

Customers, vendors, and universities (panel): determining the future of EDA together

Asynchronous interface specification, analysis and synthesis

Automatic synthesis of interfaces between incompatible protocols

Automated composition of hardware components

Multilevel integral equation methods for the extraction of substrate coupling parameters in mixed-signal IC's

Phase noise in oscillators: a unifying theory and numerical methods for characterisation

Efficient analog test methodology based on adaptive algorithms

General AC constraint transformation for analog ICs

Design methodology used in a single-chip CMOS 900 MHz spread-spectrum wireless transceiver

A video signal processor for MIMD multiprocessing

Realization of a programmable parallel DSP for high performance image processing applications

A multiprocessor DSP system using PADDI-2

Design and implementation of the NUMAchine multiprocessor

Design and specification of embedded systems in Java using successive, formal refinement

Efficient system exploration and synthesis of applications with dynamic data storage and intensive data transfer

Design space exploration algorithm for heterogeneous multi-processor embedded system design

Modal processes: towards enhanced retargetability through control composition of distributed embedded systems

Design methodologies for noise in digital integrated circuits

Taming noise in deep submicron digital integrated circuits (panel)

FACT: a framework for the application of throughput and power optimizing transformations to control-flow intensive behavioral descriptions

Incorporating speculative execution into scheduling of control-flow intensive behavioral descriptions

The DT-model: high-level synthesis using data transfers

Rate Optimal VLSI Design from Data Flow Graph

Planning for performance

A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together

Framework encapsulations: a new approach to CAD tool interoperability

A geographically distributed framework for embedded system design and validation

WELD—an environment for Web-based electronic design

OCCOM: efficient computation of observability-based code coverage metrics for functional verification

User defined coverage—a tool supported methodology for design verification

Enhanced visibility and performance in functional verification by reconstruction

Virtual chip: making functional models work on real target systems

Hardware/software co-design (panel): the next embedded system design challenge

Power optimization of variable voltage core-based systems

Policy optimization for dynamic power management

A framework for estimation and minimizing energy dissipation of embedded HW/SW systems

Using reconfigurable computing techniques to accelerate problems in the CAD domain: a case study with Boolean satisfiability

Fast exact minimization of BDDs

Boolean matching for large libraries

A fast hierarchical algorithm for 3-D capacitance extraction

Boundary element method macromodels for 2-D hierachical capacitance extraction

Efficient thee-dimensional extraction based on static and full-wave layered Green's functions

Robust Elmore delay models suitable for full chip timing verification of a 600MHz CMOS microprocessor

A top-down design environment for developing pipelined datapaths

Validation of an architectural level power analysis technique

Design methodology of a 200MHz superscalar microprocessor: SH-4

How much analog does a designer need to know for successful mixed-signal design? (panel)

Hierarchical algorithms for assessing probabilistic constraints on system performance

A tool for performance estimation of networked embedded end-systems

Rate derivation and its applications to reactive, real-time embedded systems

Generic global placement and floorplanning

Congestion driven quadratic placement

Potential-NRG: placement with incomplete data

Performance-driven multi-FPGA partitioning using functional clustering and replication

Multi-pad power/ground network design for uniform distribution of ground bounce

Layout extraction and verification methodology CMOS I/O circuits

A mixed nodal-mesh formulation for efficient extraction and passive reduced-order modeling of 3D interconnects

Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis

A methodology for guided behavioral-level optimization

A programming environment for the design of complex high speed ASICs

Media architecture: general purpose vs. multiple application-specific programmable processor

User experience with high level formal verification (panel)

What's between simulation and formal verification? (extended abstract)

Optimal FPGA mapping and retiming with efficient initial state computation

M32: a constructive multilevel logic synthesis system

Efficient Boolean division and substitution

Delay-optimal technology mapping by DAG covering

A fast fanout optimization algorithm for near-continuous buffer libraries

Performance driven multi-layer general area routing for PCB/MCM designs

Buffer insertion for noise and delay optimization

Table-lookup methods for improved performance-driven routing

Global routing with crosstalk constraints

Timing and crosstalk driven area routing

Process multi-circuit optimization

Migration: a new technique to improve synthesized designs through incremental customization

A practical repeater insertion method in high speed VLSI circuits

Practical experiences with standard-cell based datapath design tools: do we really need regular layouts?

A statistical performance simulation methodology for VLSI circuits

RF IC design challenges

Tools and methodology for RF IC design

Electromagnetic modeling and signal integrity simulation of power/ground networks in high speed digital packages and printed circuit boards

Efficient coloring of a large spectrum of graphs

Arithmetic optimization using carry-save-adders

Synthesis of power-optimized and area-optimized circuits from hierarchical behavioral descriptions

Approximation and decomposition of binary decision diagrams

Approximate reachability with BDDs using overlapping projections

Incremental CTL model checking using BDD subsetting

PRIMO: probability interpretation of moments for delay calculation

ftd: an exact frequency to time domain conversion for reduced order RLC interconnect models

Extending moment computation to 2-port circuit representations

Adjoint transient sensitivity computation in piecewise linear simulation

Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques

Design and optimization of low voltage high performance dual threshold CMOS circuits

MTCMOS hierarchical sizing based on mutual exclusive discharge patterns

Technical challenges of IP and system-on-chip (panel): the ASIC vendor perspective

Software synthesis of process-based concurrent programs

Don't care-based BDD minimization for embedded software

Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator

Code compression for embedded systems

A decision procedure for bit-vector arithmetic

Functional vector generation for HDL models using linear programming and 3-satisfiability

Automatic generation of assertions for formal verification of PowerPC microprocessor arrays using symbolic trajectory evaluation

Combining theorem proving and trajectory evaluation in an industrial environment

A fast and low cost testing technique for core-based system-on-chip

Introducing redundant computations in a behavior for reducing BIST resources

A BIST scheme for RTL controller-data paths based on symbolic testability analysis

Figures of merit to characterize the importance of on-chip inductance

Layout techniques for minimizing on-chip interconnect self inductance

A practical approach to static signal electromigration analysis

Design productivity (panel): how to measure it, how to improve it

Hierarchical functional timing analysis

Making complex timing relationships readable: Presburger formula simplicication using don't cares

Delay estimation VLSI circuits from a high-level view

TETA: transistor-level engine for timing analysis

Validation with guided search of the state space

Efficient state classification of finite state Markov chains

An implicit algorithm for finding steady states and its application to FSM verification

Hybrid verification using saturated simulation

Fast state verification

A fast sequential learning technique for real circuits with application to enhancing ATPG performance

Fault-simulation based design error diagnosis for sequential circuits

Functional verification of a multiple-issue, out-of-order, superscalar Alpha processor—the DEC Alpha 21264 microprocessor

Design reliability—estimation through statistical analysis of bug discovery data

Functional verification of large ASICs

The EDA start-up experience (panel): the first product

Digital system simulation: methodologies and examples

Hybrid techniques for fast functional simulation

A reconfigurable logic machine for fast event-driven simulation

Parallel algorithms for power estimation

A power macromodeling technique based on power sensitivity

Maximum power estimation using the limiting distributions of extreme order statistics

An optimization-based error calculation for statistical power estimation of CMOS logic circuits

Using complementation and resequencing to minimize transitions

Technology mapping for large complex PLDs

Delay-optimal technology mapping for FPGAs with heterogeneous LUTs

Exact tree-based FPGA technology mapping for logic blocks with independent LUTs

Compatible class encoding in hyper-function decomposition for FPGA synthesis

In-place power optimization for LUT-based FPGAs

A re-engineering approach to low power FPGA design using SPFD

Power considerations in the design of the Alpha 21264 microprocessor

Reducing power in high-performance microprocessors

Design and analysis of power distribution networks in PowerPC microprocessors

Full-chip verification methods for DSM power distribution systems

System chip test challenges, are there solutions today? (panel)

System-chip test strategies

Finite state machine decomposition for low power

Computational kernels and their application to sequential power optimization

Partitioning and optimizing controllers synthesized from hierarchical high-level descriptions

Watermarking techniques for intellectual property protection

Robust IP watermarking methodologies for physical design

Data security for Web-based CAD

Design of a SPDIF receiver using protocol compiler

MetaCore: an application specific DSP development system

A case study in embedded system design: an engine control unit

HW/SW coverification performance estimation and benchmark for a 24 embedded RISC core design

System-level exploration with SpecSyn

Presentations from the 35th DAC: 35 years of design automation

A methodology for guided behavioral-level optimization

Content Provider	ACM Digital Library
Author	Guerra, Lisa Potkonjak, Miodrag Rabaey, Jan
Abstract	Optimization at the early stages of design are crucial. However, due to an overwhelming number of design and optimization options, design exploration is often conducted in a qualitative, ad-hoc manner. This paper presents a methodology and interactive environment for guiding the exploration process. A prototype targeting behavioral-level optimization for datapath-intensive ASIC implementations has been developed. The key to the approach is encapsulated knowledge about the various optimizations and a set of techniques to automatically extract the “essence” of a design description. At each stage in the exploration process, the system suggests and ranks potential optimizations, both in terms of immediate and longer-term impact. It also provides evaluations of the design and of the likely affects each optimization will have on metrics like power and performance. In the new approach, the designer is responsible for making the actual optimization selections. However, using the provide guidance, designers can make decisions in a more informed manner, and therefore can explore the design solution space more effectively. The effectiveness of the approach is demonstrated on a number of designs.
Starting Page	309
Ending Page	314
Page Count	6
File Format	PDF
ISBN	0897919645
DOI	10.1145/277044.277134
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1998-05-01
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Congestion global routing quadratic placement relaxed pins routing models supply-demand
Content Type	Text
Resource Type	Article

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