NDLI: On path selection in combinational logic circuits

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Future developments in information technology (abstract)

Twenty-five years of electronic design automation

An automated BIST approach for general sequential logic synthesis

Automatic insertion of BIST hardware using VHDL

VLSI design synthesis with testability

A defect-tolerant and fully testable PLA

The role of VHDL in the MCC CAD system

VHDL: a call for standards

Verification of VHDL designs using VAL

A module area estimator for VLSI layout

A new area and shape function estimation technique for VLSI layouts

Optimal aspect ratios of building blocks in VLSI

Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing

Automating the design of electronic packaging (tutorial)

Opportunities in computer integrated manufacturing

Contest: a concurrent test generator for sequential circuits

A method of delay fault test generation

Split circuit model for test generation

A notation for describing multiple views of VLSI circuits

A graphical hardware design language

A human machine interface for silicon compilation

Parallel placement on reduced array architecture

Parallel channel routing

Mask verification on the connection machine

Future computing environments for DA (panel)

On path selection in combinational logic circuits

Pearl: a CMOS timing analyzer

ATV: an abstract timing verifier

An empirical study of on-chip parallelism

Parallel logic simulation on general purpose machines

A programmable hardware accelerator for compiled electrical simulation

Recursive channel router

Multi-pads, single layer power net routing in VLSI circuits

LocusRoute: a parallel global router for standard cells

Behavioral modeling for system design (panel)

Formal specification and verification of hardware: a comparative case study

Proving circuit correctness using formal comparison between expected and extracted behaviour

Formal verification of the Sobel image processing chip

The IBM engineering verification engine

Logic simulation system using simulation processor (SP)

Algorithm for vectorizing logic simulation and evaluation of “VELVET” performance

A structural representation for VLSI design

Parameterized schematics

Patchwork: layout from schematic annotations

What is a design automation framework, anyway? (panel)

A database management system for a VLSI design system

An enhanced data model for CAD/CAM database systems

Browsing in chip design database

Versions and change notification in an object-oriented database system

An accurate and efficient gate level delay calculator for MOS circuits

Delay modeling and time of bipolar digital circuits

Pattern-independent current estimation for reliability analysis of CMOS circuits

Improved methods of simulating RLC couple and uncoupled transmission lines based on the method of characteristics

Performance of a new annealing schedule

Clustering based simulated annealing for standard cell placement

Proud: a fast sea-of-gates placement algorithm

A quadratic metric with a simple solution scheme for initial placement

Tutorial on high-level synthesis

The system architect's workbench

A context mechanism to control sharing in a design database

Object type oriented data modeling for VLSI data management

Concurrency control in a VLSI design database

Automated design software for switched-capacitor IC's with symbolic simulator SCYMBAL

Analog compilation based on successive decompositions

Model development and verification for high level analog blocks

Symbolic layout compaction review

Compaction with incremental over-constraint resolution

An efficient compactor for 45° layout

MILO: a microarchitecture and logic optimizer

BECOME: behavior level circuit synthesis based on structure mapping

Bridge: a versatile behavioral synthesis system

PLAYGROUND: minimization of PLAs with mixed ground true outputs

A fast algorithm to minimize multi-output mixed-polarity generalized Reed-Muller forms

A kernel-finding state assignment algorithm for multi-level logic

A high packing density module generator for CMOS logic cells

SOLO: a generator of efficient layouts from optimized MOS circuit schematics

An electrical optimizer that considers physical layout

Analyzing CMOS power supply networks using Ariel

RISCE—a reduced instruction set circuit extractor for hierarchical VLSI layout verification

Time efficient VLSI artwork analysis algorithms in GOALIE2

CAD tool needs for system designers

High-level synthesis: current status and future directions

HERCULES—a system for high-level synthesis

Design process model in the Yorktown Silicon Compiler

Fast incremental circuit analysis using extracted hierarchy

Incremental-in-time algorithm for digital simulation

A dynamically-directed switch model for MOS logic simulation

A circuit comparison system with rule-based functional isomorphism checking

LOGEX—an automatic logic extractor form transistor to gate level for CMOS technology

A Prolog-based connectivity verification tool

Will cell generation displace standard cells?

CORAL II: linking behavior and structure in an IC design system

Splicer: a heuristic approach to connectivity binding

Module selection for pipelined synthesis

The use of Petri nets for modeling pipelined processors

Fast algorithm for optimal layer assignment

Connectivity biased channel construction and ordering for building-block layout

A new approach to the pin assignment problem

The constrained via minimization problem for PCB and VLSI design

Micro-operation perturbations in chip level fault modeling

A new two task algorithm for clock mode fault simulation in sequential circuits

Switch level random pattern testability analysis

Dytest: a self-learning algorithm using dynamic testability measures to accelerate test generation

CATAPULT: concurrent automatic testing allowing parallelization and using limited topology

A graph compaction approach to fault simulation

Automatic functional test program generation for microprocessors

Spare allocation and reconfiguration in large area VLSI

A data structure for circuit net lists

The architecture of a highly integrated simulation system

Circuit compilers don't have to be slow

Constraint propagation in an object-oriented IC design environment

Design automation for the component parts industry

Automatic building of graphs for rectangular dualisation

Automatic layout procedures for serial routing devices

A digit-serial silicon compiler

DECOMPOSER: a synthesizer for systolic systems

SMART: tools and methods for synthesis of VLSI chips with processor architecture

Routing algorithm for gate array macro cells

How to obtain more compactable channel routing solutions

A channelless, multilayer router

An interactive maze router with hints

Improved channel routing by via minimization and shifting

The Min-cut shuffle: toward a solution for the global effect problem of Min-cut placement

Fault simulation in a distributed environment

The performance of the concurrent fault simulation algorithms in MOZART

An approach to fast hierarchical fault simulation

Why partial design verification works better than it should

Advances in functional abstraction from structure

Hardware logic simulation by compilation

Clock even suppression algorithm of VELVET and its application to S-820 development

A path selection algorithm for timing analysis

Algorithms for timing requirement analysis and generation

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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