NDLI: Filtering Techniques to Improve Trace-Cache Efficiency

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Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications

Modeling Superscalar Processors via Statistical Simulation

Hybrid Analytical-Statistical Modeling for Efficiently Exploring Architecture and Workload Design Spaces

Filtering Techniques to Improve Trace-Cache Efficiency

Reactive-Associative Caches

Adaptive Mode Control: A Static-Power-Efficient Cache Design

Implementation and Evaluation of the Complex Streamed Instruction Set

On the Efficiency of Reductions in µ-SIMD Media Extensions

Boolean Formula-Based Branch Prediction for Future Technologies

Using Dataflow Based Context for Accurate Value Prediction

Recovery Mechanism for Latency Misprediction

A Cost Framework for Evaluating Integrated Restructuring Optimizations

Compiling for the Impulse Memory Controller

On the Stability of Temporal Data Reference Profiles

Code Reordering and Speculation Support for Dynamic Optimization System

A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors

Cache-Friendly Implementations of Transitive Closure

Exploring the Design Space of Future CMPs

Area and System Clock Effects on SMT/CMP Processors

Limits on Speculative Module-Level Parallelism in Imperative and Object-Oriented Programs on CMP Platforms

Compiler and Runtime Analysis for Efficient Communication in Data Intensive Applications

Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors

Optimizing Software Data Prefetches with Rotating Registers

Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism for Pointer-Chasing Codes

Data Flow Analysis for Software Prefetching Linked Data Structures in Java

Comparing and Combining Read Miss Clustering and Software Prefetching

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Filtering Techniques to Improve Trace-Cache Efficiency

Content Provider	ACM Digital Library
Author	Mendelson, Avi Rosner, Roni Ronen, Ronny
Abstract	Abstract: The trace cache is becoming an important building block of modern, wide-issue processors. So far, trace cache related research has been focused on increasing fetch bandwidth. Trace-caches have been shown too effectively increase the number of "useful" instructions that can be fetched into the machine, thus enabling more instructions to be executed each cycle. However, trace cache has another important benefit that got less attention in recent research: especially for variable length ISA, such as Intel's IA-32 architecture (X86), reducing instruction decoding power is particularly attractive. Keeping the instruction traces in decoded format, implies the decoding power is only paid upon the build of a trace, thus reducing the overall power consumption of the system. This paper has three main contributions: it indicates that trace cache optimizations directed to reducing power consumption arc do not necessarily coincide with optimizations directed to increasing fetch bandwidth; it extends our understanding on how well the trace cache utilizes its resources and introduces a new trace-cache organization based on filtering techniques. The knowledge obtained from the analysis of the traces' behavioral patterns motivates the use of filtering techniques. The new trace-cache organization increases the effective instruction-fetch bandwidth in conjunction with reducing the power consumption of the trace-cache system. We observe that (1) the majority of traces that are inserted into the trace-cache are rarely used again before being replaced; (2) the majority of the instructions delivered for execution originate from the fewer traces that are heavily and repeatedly used; and that (3) techniques that aim to improve instruction-fetch bandwidth may increase the number of traces built during program execution. Based on these observations, we propose splitting the trace cache into two components: the filter trace-cache (FTC) and the main trace-cache (MTC). Traces are first inserted into the FTC that is used to filter out the infrequently used traces; traces that prove "useful" are later moved into the MTC itself. The FTC/MTC organization exhibits an important benefit: it decreases the number of traces built, thus reducing power consumption while improving overall performance. For medium-size applications, the FTC/MTC pair reduces the number of trace builds by 16% in average. As extension of the filtering concept that involves adding a second level (L2) trace-cache that stores less frequent traces that are replaced in the FTC or the MTC. The extra level of caching allows for order-of-magnitude reduction in the number of trace builds. Second level trace cache proves particularly useful for applications with large instruction footprints.
Starting Page	37
Ending Page	48
Page Count	12
ISBN	0769513638
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2001-09-08
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Filtering techniques to improve trace-cache efficiency

Filtering Techniques to Improve Trace-Cache Efficiency (2001)

Hardware techniques to improve cache efficiency

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Rank-aware cache replacement and write buffering to improve DRAM energy efficiency

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Filtering Techniques to Improve Trace-Cache Efficiency

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