NDLI: Speeding up machine-code synthesis

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Speeding up machine-code synthesis

Content Provider	ACM Digital Library
Author	Sharma, Tushar Reps, Thomas Srinivasan, Venkatesh
Abstract	Machine-code synthesis is the problem of searching for an instruction sequence that implements a semantic specification, given as a formula in quantifier-free bit-vector logic (QFBV). Instruction sets like Intel's IA-32 have around 43,000 unique instruction schemas; this huge instruction pool, along with the exponential cost inherent in enumerative synthesis, results in an enormous search space for a machine-code synthesizer: even for relatively small specifications, the synthesizer might take several hours or days to find an implementation. In this paper, we present several improvements to the algorithms used in a state-of-the-art machine-code synthesizer McSynth. In addition to a novel pruning heuristic, our improvements incorporate a number of ideas known from the literature, which we adapt in novel ways for the purpose of speeding up machine-code synthesis. Our experiments for Intel's IA-32 instruction set show that our improvements enable synthesis of code for 12 out of 14 formulas on which McSynth times out, speeding up the synthesis time by at least 1981X, and for the remaining formulas, speeds up synthesis by 3X. .
Starting Page	165
Ending Page	180
Page Count	16
File Format	PDF
ISBN	9781450344449
DOI	10.1145/2983990.2984006
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-10-19
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Machine-code synthesis Ia-32 instruction set Flattening deep terms Flow independence Move-to-front heuristic Pruning heuristics
Content Type	Text
Resource Type	Article

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