NDLI: Efficient Timestamp-Based Cache Coherence Protocol for Many-Core Architectures

Please wait, while we are loading the content...

Polly-ACC Transparent compilation to heterogeneous hardware

AEQUITAS: Coordinated Energy Management Across Parallel Applications

Mini-Ckpts: Surviving OS Failures in Persistent Memory

HOPE: Enabling Efficient Service Orchestration in Software-Defined Data Centers

Coherence-Free Multiview: Enabling Reference-Discerning Data Placement on GPU

SReplay: Deterministic Sub-Group Replay for One-Sided Communication

BLASX: A High Performance Level-3 BLAS Library for Heterogeneous Multi-GPU Computing

Proteus: Exploiting Numerical Precision Variability in Deep Neural Networks

TokenTLB: A Token-Based Page Classification Approach

Fairness-oriented OS Scheduling Support for Multicore Systems

DSMR: A Parallel Algorithm for Single-Source Shortest Path Problem

Fast Multiplication in Binary Fields on GPUs via Register Cache

TurboTiling: Leveraging Prefetching to Boost Performance of Tiled Codes

Origami: Folding Warps for Energy Efficient GPUs

Hybrid CPU-GPU scheduling and execution of tree traversals

Runtime-Guided Mitigation of Manufacturing Variability in Power-Constrained Multi-Socket NUMA Nodes

High Performance Design for HDFS with Byte-Addressability of NVM and RDMA

Towards an Adaptive Multi-Power-Source Datacenter

SFU-Driven Transparent Approximation Acceleration on GPUs

Lynx: Using OS and Hardware Support for Fast Fine-Grained Inter-Core Communication

Peruse and Profit: Estimating the Accelerability of Loops

Galaxyfly: A Novel Family of Flexible-Radix Low-Diameter Topologies for Large-Scales Interconnection Networks

Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration

Scheduling Tasks with Mixed Timing Constraints in GPU-Powered Real-Time Systems

Parallel Transposition of Sparse Data Structures

Balanced Hashing and Efficient GPU Sparse General Matrix-Matrix Multiplication

Graph Prefetching Using Data Structure Knowledge

Barrier-Aware Warp Scheduling for Throughput Processors

Exploiting Dynamic Reuse Probability to Manage Shared Last-level Caches in CPU-GPU Heterogeneous Processors

Variation Among Processors Under Turbo Boost in HPC Systems

Write-Aware Management of NVM-based Memory Extensions

GreenGear: Leveraging and Managing Server Heterogeneity for Improving Energy Efficiency in Green Data Centers

Reusing Data Reorganization for Efficient SIMD Parallelization of Adaptive Irregular Applications

Efficient Timestamp-Based Cache Coherence Protocol for Many-Core Architectures

Simulation and Analysis Engine for Scale-Out Workloads

Replichard: Towards Tradeoff between Consistency and Performance for Metadata

GCaR: Garbage Collection aware Cache Management with Improved Performance for Flash-based SSDs

CuMAS: Data Transfer Aware Multi-Application Scheduling for Shared GPUs

SARVAVID: A Domain Specific Language for Developing Scalable Computational Genomics Applications

Optimizing Sparse Matrix-Vector Multiplication for Large-Scale Data Analytics

Prefetching Techniques for Near-memory Throughput Processors

Tag-Split Cache for Efficient GPGPU Cache Utilization

Noise Aware Scheduling in Data Centers

Efficient Timestamp-Based Cache Coherence Protocol for Many-Core Architectures

Content Provider	ACM Digital Library
Author	Wang, Guanhua Ge, Zhiguo Chen, Wenzhi Yao, Yuan Zhang, Naxin Mitra, Tulika
Abstract	As we enter the era of many-core, providing the shared memory abstraction through cache coherence has become progressively difficult. The de-facto standard directory-based cache coherence has been extensively studied; but it does not scale well with increasing core count. Timestamp-based hardware coherence protocols introduced recently offer an attractive alternative solution. In this paper, we propose a timestamp-based coherence protocol, called TC-Release++, that addresses the scalability issues of efficiently supporting cache coherence in large-scale systems. Our approach is inspired by TC-Weak, a recently proposed timestamp-based coherence protocol targeting GPU architectures. We first design TC-Release coherence in an attempt to straightforwardly port TC-Weak to general-purpose many-cores. But re-purposing TC-Weak for general-purpose many-core architectures is challenging due to significant differences both in architecture and the programming model. Indeed the performance of TC-Release turns out to be worse than conventional directory coherence protocols. We overcome the limitations and overheads of TC-Release by introducing simple hardware support to eliminate frequent memory stalls, and an optimized life-time prediction mechanism to improve cache performance. The resulting optimized coherence protocol TC-Release++ is highly scalable (overhead for coherence per last-level cache line scales logarithmically with core count as opposed to linearly for directory coherence) and shows better execution time (3.0%) and comparable network traffic (within 1.3%) relative to the baseline MESI directory coherence protocol.
Starting Page	1
Ending Page	13
Page Count	13
File Format	PDF
ISBN	9781450343619
DOI	10.1145/2925426.2926270
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-06-01
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in