NDLI: Bandwidth-optimal all-to-all exchanges in fat tree networks

Please wait, while we are loading the content...

Business meets supercomputing: keynote talk

Abstractions to separate concerns in semi-regular grids

TEAPOT: a toolset for evaluating performance, power and image quality on mobile graphics systems

Conservative row activation to improve memory power efficiency

Function, latency, bandwidth, power: towards a better computer

Improving communication in PGAS environments: static and dynamic coalescing in UPC

Exploring hardware overprovisioning in power-constrained, high performance computing

Improving numerical accuracy for non-negative matrix multiplication on GPUs using recursive algorithms

Tuning the continual flow pipeline architecture

Efficient sparse matrix-vector multiplication on x86-based many-core processors

Diagnosis and optimization of application prefetching performance

The role of computer designers in reverse-engineering the brain

Holistic run-time parallelism management for time and energy efficiency

CMP off-chip bandwidth scheduling guided by instruction criticality

Efficient scheduling of recursive control flow on GPUs

Hybrid approach for data-flow analysis of MPI programs

A stencil compiler for short-vector SIMD architectures

Scaling data race detection for partitioned global address space programs

Active disk meets flash: a case for intelligent SSDs

Bandwidth-optimal all-to-all exchanges in fat tree networks

The power 775 architecture at scale

Toward a scalable multi-GPU eigensolver via compute-intensive kernels and efficient communication

Towards more efficient execution: a decoupled access-execute approach

Expressing graph algorithms using generalized active messages

Address-aware fences

G-Charm: an adaptive runtime system for message-driven parallel applications on hybrid systems

Massively parallel loading

SemCache: semantics-aware caching for efficient GPU offloading

Improving performance of all-to-all communication through loop scheduling in PGAS environments

Exploiting domain knowledge to optimize parallel computational mechanics codes

Elastic and scalable tracing and accurate replay of non-deterministic events

Design of a large-scale storage-class RRAM system

An automatic input-sensitive approach for heterogeneous task partitioning

Bubble coloring: avoiding routing- and protocol-induced deadlocks with minimal virtual channel requirement

High quality real-time image-to-mesh conversion for finite element simulations

Quantifying performance bottleneck cost through differential analysis

HykSort: a new variant of hypercube quicksort on distributed memory architectures

Prefetching and cache management using task lifetimes

Implementing OmpSs support for regions of data in architectures with multiple address spaces

MIC-RO: enabling efficient remote offload on heterogeneous many integrated core (MIC) clusters with InfiniBand

Exploiting uniform vector instructions for GPGPU performance, energy efficiency, and opportunistic reliability enhancement

CUPL: a compile-time uncoalesced memory access pattern locator for CUDA

A new approach for performance analysis of openMP programs

Memorage: emerging persistent RAM based malleable main memory and storage architecture

LibWater: heterogeneous distributed computing made easy

Evaluating on-die interconnects for a 4 TB/s router

Automatically adapting programs for mixed-precision floating-point computation

Scaling large-data computations on multi-GPU accelerators

Imbalance optimization in scientific workflows

FASTER run-time reconfiguration management

MAD7: a memory architecture simulator targeted at design space exploration

A decomposition method with minimal communication volume for parallelization of multi-dimensional FFTs

A massively parallel domain decomposition method for large-scale DFT electronic structure calculations

Multi-layered unstructured mesh generation

Network-on-chip for a partially reconfigurable FPGA system

Exploiting data parallelism in the yConvex hypergraph algorithm for image representation using GPGPUs

The ARMv8 simulator

Imogen: a parallel 3D fluid and MHD code for GPUs

SMIO: I/O similarity aware virtual machine management invirtual desktop environments

Inspector/executor load balancing algorithms for block-sparse tensor contractions

Improving performance of openSHMEM reference library by portable PE mapping technique

Using platform-independent data locality analysis to predict cache performance on abstract hardware platforms

Towards shared memory consistency models for GPUs

Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches

V-OpenCL: a method to use remote GPGPU

Power efficiency in a partially reconfigurable multiprocessor system

Bandwidth-optimal all-to-all exchanges in fat tree networks

Content Provider	ACM Digital Library
Author	Rodriguez, German Prisacari, Bogdan Minkenberg, Cyriel Hoefler, Torsten
Abstract	The personalized all-to-all collective exchange is one of the most challenging communication patterns in HPC applications in terms of performance and scalability. In the context of the fat tree family of interconnection networks, widely used in current HPC systems and datacenters, we show that there is potential for optimizing this traffic pattern by deriving a tight theoretical lower bound for the bandwidth needed in the network to support such communication in a non-contending way. Current state of the art methods require up to twice as much bisection bandwidth as this theoretical minimum. We propose a set of optimized exchanges that use exactly the minimum amount of resources and exhibit close to ideal performance. This enables cost-effective networks, i.e., with as little as half the bisection bandwidth required by current state of the art methods, to exhibit quasi optimal performance under all-to-all traffic. In addition to supporting our claims by mathematical proofs, we include simulation results that confirm their correctness in practical system configurations.
Starting Page	139
Ending Page	148
Page Count	10
File Format	PDF
ISBN	9781450321303
DOI	10.1145/2464996.2465434
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-06-10
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Bandwidth optimality Fat tree networks All-to-all
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in