NDLI: PWAM signalling scheme for high speed serial link transceiver design

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Design approaches for hybrid CMOS/molecular memory based on experimental device data

HW/SW partitioning techniques for multi-mode multi-task embedded applications

PWAM signalling scheme for high speed serial link transceiver design

Dominator-based partitioning for delay optimization

Delay and Power Estimation Models of Low-Swing Interconnects for Design Planning

Maximum effective distance of on-chip decoupling capacitors in power distribution grids

Sensitivity evaluation of global resonant H-tree clock distribution networks

Techniques for improved placement-coupled logic replication

An indirect current sensing technique for IDDQ and IDDT tests

Using Lin-Kernighan algorithm for look-up table compression to improve code density

Monotonic static CMOS tradeoffs in sub-100nm technologies

Evaluation of on-chip networks using deflection routing

Selective code/data migration for reducing communication energy in embedded MpSoC architectures

A design methodology for temperature variation insensitive low power circuits

DFM: swimming upstream

Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations

ISS-centric modular HW/SW co-simulation

High speed differential pulse-width control loop based on frequency-to-voltage converters

How does partitioning matter for 3D floorplanning?

A simulation methodology for reliability analysis in multi-core SoCs

Implementation of MOSFET based capacitors for digital applications

2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology

A design flow to optimize circuit delay by using standard cells and PLAs

SACI: statistical static timing analysis of coupled interconnects

FPGA implementation of a parallel EBCOT tier-1 encoder that preserves coding efficiency

A power optimized design methodology for low-distortion sigma-delta-pipeline ADCs

A digit serial algorithm for the integer power operation

Dynamic voltage scaling for multitasking real-time systems with uncertain execution time

Circuit architecture for low-power race-free programmable logic arrays

From single core to multi-core to many core: are we ready for a new exponential?

Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies

An ILP based approach to address code generation for digital signal processors

Synthesis of a wideband low noise amplifier

Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs

Power density minimization for highly-associative caches in embedded processors

Efficient modeling of integrated narrow-band low noise amplifiers for design space exploration

Implementation analysis of NoC: a MPSoC trace-driven approach

Statistical gate delay calculation with crosstalk alignment consideration

Performance verification of high-performance ASICs using at-speed structural test

Partial parallel factorization in soft-decision Reed-Solomon decoding

Perception-guided power minimization for color sequential displays

Resource and delay efficient matrix multiplication using newer FPGA devices

Low-power cache organization through selective tag translation for embedded processors with virtual memory support

An energy-efficient temporal encoding circuit technique for on-chip high performance buses

Thermal analysis of a 3D die-stacked high-performance microprocessor

HW/SW co-verification of embedded systems using bounded model checking

A $0.13_{μm}$ CMOS 10 Gb/s current-mode class AB serial link transmitter with low supply voltage sensitivity

Shuttle mask floorplanning with modified alpha-restricted grid

An evaluation of the impact of gate oxide tunneling on $dual-V_{t}-based$ leakage reduction techniques

Towards formal probabilistic power-performance design space exploration

Crosstalk analysis in nanometer technologies

Parallel turbo-sum-product decoder architecture for quasi-cyclic LDPC codes

STV-Cache: a leakage energy-efficient architecture for data caches

Leakage current starved domino logic

Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction

Energy-delay minimization in nanoscale domino logic

General transistor-level methodology on VLSI low-power design

High throughput architecture for H.264/AVC forward transforms block

Delay and peak power minimization for on-chip buses using temporal redundancy

Hardware/software partitioning of operating systems: a behavioral synthesis approach

Low-noise high-precision operational amplifier using vertical NPN transistor in CMOS technology

A practical approach for monitoring analog circuits

A new power-area efficient 4-PAM full-clock CMOS pre-emphasis transmitter for 10Gb/s serial links

A non-orthogonal clock distribution network and its performance evaluation in presence of process variations and inductive effects

A low-power and high-linear double-balanced switching mixer

A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy Models

Nonlinearity Analysis in ISD CMOS LNA's Using Volterra Series

A formal approach for high level synthesis of linear analog systems

On-chip 3.3V-to-1.8V voltage down converter for low-power VLSI chips

Transformation synthesis for data intensive applications to FPGAs

A SiGe BiCMOS linear regulator with wideband, high power supply rejection

An integrated circuit/behavioral simulation framework for continuous-time sigma-delta ADCs

Optimizing noise-immune nanoscale circuits using principles of Markov random fields

A heuristic algorithm to minimize ESOPs for multiple-output incompletely specified functions

Dynamic instruction schedulers in a 3-dimensional integration technology

Test generation using SAT-based bounded model checking for validation of pipelined processors

Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology

An efficient algorithm for partitioning parameterized polygons into rectangles

Effects of process and environmental variations on timing characteristics of clocked registers

Application of fast SOCP based statistical sizing in the microprocessor design flow

On finding the minimum test set of a BDD-based circuit

Block alignment in 3D floorplan using layered TCG

Rapid intermodulation distortion estimation in fully balanced weakly nonlinear Gm-C filters using state-space modeling

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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