NDLI: Verifying start-up conditions for a ring oscillator

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Technology, CAD tools, and designs for emerging 3D integration technology

GLSVLSI 2008 invited/keynote talk

Temperature-insensitive synthesis using multi-vt libraries

NBTI-aware flip-flop characterization and design

A GF(p) elliptic curve group operator resistant against side channel attacks

Using unsatisfiable cores to debug multiple design errors

Compressor trees for decimal partial product reduction

Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty

On the design of customizable low-voltage common-gate LNA-mixer pair using current and charge reusing techniques

GLSVLSI 2008 invited/keynote talk

SAT-based equivalence checking of threshold logic designs for nanotechnologies

A novel performance driven power gating based on distributed sleep transistor network

On efficient generation of instruction sequences to test for delay defects in a processor

Scalable and fault-tolerant network-on-chip design usingthe quartered recursive diagonal torus topology

Fast bus waveform estimation at the presence of coupling noise

FEKIS: a fast architecture-level thermal analyzer for online thermal regulation

12bits 40mhz pipelined ADC with duty-correction circuit

A formula of STI cmp design rule

On-die CMOS voltage droop detection and dynamiccompensation

Reconfigurable solutions for very-long arithmetic with applications in cryptography

A novel test-data compression technique using application-aware bitmask and dictionary selection methods

Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits

Optimal sleep transistor synthesis under timing and area constraints

Verifying start-up conditions for a ring oscillator

Pairwise decomposition of toffoli gates in a quantum circuit

A practical repeater insertion flow

NBTI resilient circuits using adaptive body biasing

A lithography-friendly structured ASIC design approach

Mesh-of-tree deterministic routing for network-on-chip architecture

An analytical model for the upper bound on temperature differences on a chip

Comparison of redundant architectures for two-step ADCs

Considering possible opens in non-tree topology wire delay calculation

Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators

Fast composite field S-box architectures for advanced encryption standard

HyMacs: hybrid memory access optimization based on custom-instruction scheduling

A high-speed radix-4 multiplexer-based array multiplier

Energy efficiency bounds of pulse-encoded buses

A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm

Design of defect tolerant tile-based QCA circuits

Criticality history guided FPGA placement algorithm for timing optimization

A tool flow for predicting system level timing failures due to interconnect reliability degradation

Efficient tree topology for FPGA interconnect network

Fpga-based hardware/software co-design for chirplet signal decomposition

Power management of variation aware chip multiprocessors

Nonuniformly quantized min-sum decoder architecture for low-density parity-check codes

Variational capacitance modeling using orthogonal polynomial method

A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip

A table-based method for single-pass cache optimization

Automated formal verification of scheduling with speculative code motions

A robust, fast pulsed flip-flop design

Implementation of asynchronous pipeline circuits in multi-threshold CMOS technologies

Pipelined network of PLA based circuit design

A layout-aware physical design method for constructing feasible QCA circuits

A linear programming formulation for security-aware gate sizing

Statistically translating low-level error probabilities to increase the accuracy and efficiency of reliability simulations in hardware description languages

Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater count

Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip

Low-power clock distribution in a multilayer core 3d microprocessor

Extended layered decoding of LDPC codes

Statistical timing analysis of flip-flops considering codependent setup and hold times

A low leakage 9t sram cell for ultra-low power operation

A low-power 12-bit 80MHz CMOS DAC using pseudo-segmentation

A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays

Improved ber performance in intra-chip rf/wireless interconnect systems

Mlp neural network and on-line backpropagation learning implementation in a low-cost fpga

Using reiterative LFSR based X-masking to increase output compression in presence of unknowns

Energy efficient synchronization techniques for embedded architectures

New technique in design of active rf cmos mixers for low flicker noise and high conversion gain

Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow

Recursion flattening

Guided test generation for isolation and detection of embedded trojans in ics

Quick supply current waveform estimation at gate level using existed cell library information

Electrical models for vertical carbon nanotube capacitors

Coverage-driven automatic test generation for uml activity diagrams

In-order pulsed charge recycling in off-chip data buses

Hardware/software partitioning with multi-version implementation exploration

An energy-aware co-simulation framework for the design of wireless sensor networks

Improving FPGA routability using network coding

Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy

Impact of dummy filling techniques on interconnect capacitance and planarization in nano-scale process technology

Instruction cache leakage reduction by changing register operands and using asymmetric sram cells

Energy saving for memory with loop scheduling and prefetching

Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --

A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection

Full-chip leakage current estimation based on statistical sampling techniques

Delay driven AIG restructuring using slack budget management

A low-power phase change memory based hybrid cache architecture

An analytical approach to placement legalization

Exploiting frequent opcode locality for power efficient instruction cache

Simultaneous optimization of memory configuration and code allocation for low power embedded systems

Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms

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